The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Gaussian Synapse Model Problem
https://designers-guide.org/forum/YaBB.pl?num=1110816294

Message started by Vikram Srinivasan on Mar 14^th, 2005, 8:04am

Title: Gaussian Synapse Model Problem
Post by Vikram Srinivasan on Mar 14^th, 2005, 8:04am

Hello

I am trying to simulate a circuit that functions as a Gaussian activation function(in a neural network). I am using the model proposed by K.T.Lau and S.T.Lee in their paper "Analog Gaussian Synapse for Artificial Neural Networks". The circuit is composed entirely of MOS transistors and I am simulating it using the MOS model available in the Cadence Verilog Library files.

My problem is that I am not able to perform a complete simulation,since current values exceed the permissible limits during simulation. I have verified all my connections and my source voltage values.

Since the circuit is difficult to explain in words,I am not attempting that here. If somebody can help me, I can forward the circuit and codes to you so you can take a look and try identifying what could be the problem. You can contact me through my email ( vikramts@yahoo.com ).

I could really use some help here! Any assistance is greatly appreciated !!!!!

this is a circuit to produce a Gaussian activation function for a neuron. I am using the cmos model provided by cadence for this ckt and I know this model is accurate(since I have used it in another ckt). The model is included in the other doc I have attached.

My problem is that I am not able to perform a simulation due to voltage/current values which exceed limits at nodes. This circuit has been simulated and I have included the actual paper as a pdf file too.

Mohit suggested that I should try making it work stage-by-stage. So now , im trying to make the first transconductance amplifier(the ckt formed by 1-4-5-8-9) work. I gave a 0-0.5v input and couldn’t find any change in current at drain1(the currents flowing to 4 and 5 were found to be equal and this shouldn’t be the case).

The mos definition needs 4 port maps for drain/gate/source/bulk in that order. The dev_type is 1 for nmos and 0 for pmos. I think the code I wrote is fairly self-explanatory(the mos code is too fundooo for my understanding!)….

Can u try simulating the first stage and tell me what u get? I got the same value for current at drain9(cd9) for 0V input and for 0.5V input.

If the first stage works, we can take it from there and make the whole ckt work in steps.

Title: Re: Gaussian Synapse Model Problem
Post by vikramts on Mar 14^th, 2005, 8:07am

Haha, I posted the last 3 paragraphs by mistake(it was from another email I had sent to a friend, asking his help for the same problem!).

Please ignore that...but do try to take a look at my model and codes !

Thanks