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Other CAD Tools >> Physical Verification, Extraction and Analysis >> The extraction problem of BJT transistor
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Message started by Question on Sep 22^nd, 2004, 1:52am

Title: The extraction problem of BJT transistor
Post by Question on Sep 22^nd, 2004, 1:52am

My design environment is TSMC 0.18UM MM/RF 1P6M SALICIDE 1.8V/3.3V PROCESS PDK (for Cadence) Revision 1.1a. There are some BJT transistors in the circuit. The cell name of BJT is ' vpnp3 ', the view name is ' spectre ' in my schematic. There is no layout pcell of BJT transistor in the PDK, so I make the layout design by myself.

When I run a extraction by the diva rule in the PDK, it will give me a warning massage ' Cannot match terminal counts for vpnp3 ivpcell tsmc18rf '. Because of this problem, I can not clean the LVS. If I use Hercules to run a extraction job, I can get the right BJT transistors. The runset file of Hercules is ' LVS_Hercules_0.18um_MM_1p6m.20a '.

How can I get the right extracted view by diva rule? If I can not get the extracted symbol, how to simulate the circuit?

Thank you.

Title: Re: The extraction problem of BJT transistor
Post by sheldon on Apr 2^nd, 2005, 1:41am

Question,

Sorry my DIVA is a little bit rusty. First, shouldn't the
views in the schematic be symbols? The spectre view
is an internal stopping view and is not usually intended
to actual be put into schematic. Next, have you confirmed
the device extraction is correct, i.e., have you looked at
the save derived layers and verified all the terminals
exist? Since no p-cell exists, it is possible that something
is missing in your layout and DIVA is not extracting the
device correctly.

Best Regards,

Art Schaldenbrand

Title: Re: The extraction problem of BJT transistor
Post by Andrew Beckett on Apr 2^nd, 2005, 8:02am

I agree with Art. The chances are (I can't remember without looking at the PDK) that the spectre view has 4 terminals - the fourth being the bulk, which is an inherited connection.

It's quite possible that the Diva rules only extract 3 pins, and so using the symbol (which is what you're supposed to use in the schematic) will solve this problem.

That's my guess, anyway.

Ah, I've just realised that this error probably comes from the extraction, not the LVS, in which case the above theory wouldn't explain it (although it's probably a problem you'll hit further down the line).

Most likely your bipolar layouts do not match the way that the device is being recognised. I thought that the PDK came with layouts (not pcells though) for the bipolars - if not, I'd have thought sample layouts would be available from TSMC?

Regards,

Andrew.

Title: Re: The extraction problem of BJT transistor
Post by Robert on Jun 9^th, 2005, 11:46pm

hi,Question
i have suffered the same problem with you. i used the charter 0.35um RF CMOS process to design a bandgap, when i put the nine vpnp pcell close together, i mean that their collector terminals touch each other, then run the extraction, the error would come. so i have to seperate the pcells to pass the extraction at the cost of decreasing matching.
i doubt it is the reason of divaEXT.rul file, hope someone can help us solve this problem, thanks!

Title: Re: The extraction problem of BJT transistor
Post by Andrew Beckett on Jun 12^th, 2005, 12:34pm

Robert,

Well, it's either that you're breaking some design rules and laying out a structure in an illegal way - and hence the extract rules are not handling this (is the design DRC clean?) or it's a problem with the extract rules. It's extremely unlikely to be a tool problem.

Regards,

Andrew.

Title: Re: The extraction problem of BJT transistor
Post by Robert on Jun 13^th, 2005, 1:39am

hi,Andrew
yes, the DRC is clean,there is no any problem with it.our rule files are provided by the foundry,it is rarely the problem of the file,but i really can't understand why the collector terminals can't touch each other,it is the reason of process fabrication problem or parasitic problems?

regards

robert

Title: Re: The extraction problem of BJT transistor
Post by Andrew Beckett on Jun 13^th, 2005, 12:43pm

Without knowing the specific details of the process (which I'm not familiar with), I can't really comment. Sorry! Also, I don't really know how you've done the layout, so it would be hard to advise you even if I was familiar with the process.

Andrew.

Title: Re: The extraction problem of BJT transistor
Post by Robert on Jun 15^th, 2005, 3:01am

we utilize the charter 0.35um RF CMOS process to do our designs,it a n-well 2p4m multi-gate cmos process,which is develpped from standard coms process.it provides pdk documents,rule files,basic pcells(it provides some firm-size vpnp cells),and we do the half-custom layout,that is,the virtuoso layout xl generate raw layout automatically from schematic first, then we do the place and route jobs.

best wishes.