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Simulators >> Logic Simulators >> DESPERATELY IN NEED OF HELP
https://designers-guide.org/forum/YaBB.pl?num=1112040147

Message started by lancer on Feb 5^th, 2005, 6:23am

Title: DESPERATELY IN NEED OF HELP
Post by lancer on Feb 5^th, 2005, 6:23am

To whom It may concern,
I am currently in a digital electronics class and we are just getting exposed to Verilog. To test our knowledge of the language, we were asked to simulate logic gates using FET's. Problem is when I tried to design the basic inverter, there seemed to be logical errors even though the syntax was correct. I am wondering if there was something special about using FET's in verilog that I am unaware of.
Right now, all I know is that for nmos, the syntax is
"nmos(data, output, ctrl)" and pmos would be the same except with pmos in place of nmos. Using these , I keep getting the undefined output "z" instead of a logic 0 or 1 for all input configurations and I cannot figure out why.
If anyone can understand what the hell I am saying, please help me out... I am in a serious JAM here.

If it helps, here is code I have so far

*********************************************
module fet_inverter(in, out);

input in;
output out;

supply1 vdd;
supply0 gnd;

nmos(gnd, out, in);
pmos(out, vdd, in);

endmodule

//Test Module

module test_inverter;
reg in;
wire out;

initial
begin

$monitor("%d %b %b", $time, in, out);

in = 0;

#5 in = 1;

#10 $finish;

end

fet_inverter inst_1 (in, out);

endmodule

********************************************

The truth table this produces is as follows:

*********************************************
Time In Out
0 0 1
5 1 1
7 1 z
*****************************************
This is obviously wrong and I cannot figure out why............ HELP ME

Title: Re: DESPERATELY IN NEED OF HELP
Post by Humungus on Apr 22^nd, 2005, 12:29am

The proble with you example is that you interchanged the source and drain terminals of your transistors.

Your inverter should read

nmos (out, gnd, cntrl)
nmos (out, vdd, cntrl)

Cheers,