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Modeling >> Behavioral Models >> VerilogA handling for buses
https://designers-guide.org/forum/YaBB.pl?num=1112119341

Message started by kapylan_pallo on Mar 29^th, 2005, 10:02am

Title: VerilogA handling for buses
Post by kapylan_pallo on Mar 29^th, 2005, 10:02am

I'm admittedly a novice in verilogA and am simply looking to define an input bus in the verilogA language. For example, the verilogA 8-bit ADC in the ahdlLib library has 8 input terminals. How does one convert this to a single 8-bit bus to reduce the terminal count on the symbol?

Thanks,

KP

Title: Re: VerilogA handling for buses
Post by gsuarez on Mar 30^th, 2005, 12:03pm

I'm not an expert in Verilog-A but you can use this as an example,

module FLASH_ADC3bit(vin,vref,clk,dout);
input vin,vref,clk;
output [0:2] dout;
electrical vin,vref,clk;
electrical [0:2] dout;

George

Title: Re: VerilogA handling for buses
Post by jbdavid on Oct 2^nd, 2005, 6:09pm

NB: MOST people I have worked with have used the
0 bit as the LSB.. (and I like verilog 2001 syntax)
so
module myADC (input vin, clk, output [7:0] D);
electrical vin;
logic clk;
reg D;

always @(posedge clk) begin
// calculate the output code from V(vin);
end
endmodule.

For examples of a couple of ADC's and DAC's created this way look in the bmslib shipped with the cadence tools..
jbd