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Design Languages >> Verilog-AMS >> ncverilog simulation
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Message started by senthil on Apr 18^th, 2005, 12:58am

Title: ncverilog simulation
Post by senthil on Apr 18^th, 2005, 12:58am

HI

While simulating the ARM core using the ncverilog simulator on a HPUX machine , I am getting this error

ncsim: *internal* (rts_seghandler - SIGSEGV unexpected violation pc=0xc3b26b68 addr=0x2 )

While performing the same simulation on ther OS such as Linux and Solaris ,the above mentioned error is not occuring.

Kindly help me regarding this ...

Regards ,
Senthilvelan

Title: Re: ncverilog simulation
Post by Andrew Beckett on Apr 18^th, 2005, 4:46am

You should contact customer support. However, as a first step, you might want to try seeing if you're using the latest version - you didn't mention what version you're using.

I'd suggest trying it in the latest IUS54 ISR to see if that fixes it, then contact customer support if it doesn't.

Unfortunately the error is fairly non-specific, and so it's hard to debug from the message alone.

Regards,

Andrew.