The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> unit gain buffer problem
https://designers-guide.org/forum/YaBB.pl?num=1113897719

Message started by capri on Apr 19^th, 2005, 1:01am

Title: unit gain buffer problem
Post by capri on Apr 19^th, 2005, 1:01am

|---------------s3------+
| |-------s2-- -+
vin------s1---+--||-----+---|\ |
x I +-------+--- vout
gnd--|/

In the above typical circuit, when s2 open and s3 close, Vx, the negative node of amp will drop below vss. The problem is if I design the switch2 by a nmos transister, just like the example given by razavi's book, when Vx drop below the threshould voltage of s2 nmos, s2 will turn on again( if I add vss to nmos to cut-off the switch).
That will lead the Vout cannot follow the vin in the end.
If I want to cut the s2 completly I should add a undershoot voltage(-vdd), how can I generate -vdd? or any other ways to turn off the s2 completely?
thanks

Title: Re: unit gain buffer problem
Post by Sid on Apr 19^th, 2005, 9:48pm

Hi Capri,

You SHOULD avoid voltages below GND in your circuit if you are using a normal n-well process with GND as your "lowest power-supply" voltage. So, do not attempt to generate -Vdd.

I will assume your actual implementation is fully differential. The reason your op-amp's input common-mode (CM) voltage is going below GND is because your input signal's CM voltage (i.e. vin's CM value) is greater than the opamp's CM output voltage (vout's CM value).

Assume for discussion the common-mode DC value of vin = 1 V. Assume the common-mode DC value of vount is 0V. Hence in phase 1 when S1 and S2 are ON the voltage across capacitor CH = 0-1 = -1V.

Then when you "flip" the capacitor by turning ON s3, the CM voltage at X will go to -1 V (since the output common-mode level is forced to still be 0V by your common-mode feedback circuit).

Whatever the cause, understand that a "flip-around" amplifier will have a common-mode step at the input if the "op-amp output" and "input-signal" CM levels are not perfectly matched. You should design your opamp to tolerate this.

Sid

Title: Re: unit gain buffer problem
Post by capri on Apr 20^th, 2005, 5:22pm

Thank u for your explain, but I still dont know how to modify my opamp design to match the cm input voltage with cm output voltage. The cm input voltage is varied with different input, while the cm output voltage is a fixed value. How can I match them? By adding a 1/2VDD voltage to the positive node of opamp I can avoid the voltage below gnd, but if I have to fix the positive node to gnd, how can I modify my design? Thanks

Title: Re: unit gain buffer problem
Post by Sid on Apr 20^th, 2005, 6:24pm

Hi Capri,

I can help you better if you give me more details of your design.

1) What is your OTA architecture (i.e. op amp)? Is the input device NMOS or PMOS?

2) What range of input CM voltages does your OTA work under (i.e. all your input transistors and current sources are in the active range)? You can check this range by varying the input CM voltage and checking the minimum and maximum input CM voltages under which all transistors are still in active region with a DC operating point analysis.

3) What is your OTA's output CM voltage?

4) What are your power supplies?

5) What range of "input signal" CM voltages do you want to tolerate?

Exact numerical values will be helpful.

Thanks,
Sid

Title: Re: unit gain buffer problem
Post by capri on Apr 20^th, 2005, 7:53pm

Hi, sid
thank u for your patience

Sid wrote on Apr 20^th, 2005, 6:24pm:

Hi Capri,

I can help you better if you give me more details of your design.

1) What is your OTA architecture (i.e. op amp)? Is the input device NMOS or PMOS?
It is a two stage opa with rail to rail folded cascoded input stage, both nmos and pmos are used.

2) What range of input CM voltages does your OTA work under (i.e. all your input transistors and current sources are in the active range)? You can check this range by varying the input CM voltage and checking the minimum and maximum input CM voltages under which all transistors are still in active region with a DC operating point analysis.

so it's from 0 to vdd

3) What is your OTA's output CM voltage?

almost 0v

4) What are your power supplies?
vss:0v
vdd:5v

5) What range of "input signal" CM voltages do you want to tolerate?
0~5v

Exact numerical values will be helpful.

Thanks,
Sid

Thank you

Title: Re: unit gain buffer problem
Post by Sid on Apr 20^th, 2005, 8:40pm

1) What is your OTA architecture (i.e. op amp)? Is the input device NMOS or PMOS?
It is a two stage opa with rail to rail folded cascoded input stage, both nmos and pmos are used.

>> So, your input stage consists of a parallel of NMOS >> and PMOS (right?). Is it similar to Fig 9.48 on Pg. 326 >> of Dr. Razavi's textbook?

>> If this is the architecture you are using, then yes,
>> your input common-mode can go from 0 to 5V.
>> Ummmm interesting choice....
>> Remember the gain BW of this OTA is probably a
>> pretty strong function of input common-mode!

2) What range of input CM voltages does your OTA work under (i.e. all your input transistors and current sources are in the active range)? You can check this range by varying the input CM voltage and checking the minimum and maximum input CM voltages under which all transistors are still in active region with a DC operating point analysis.

so it's from 0 to vdd

>> Okay.

3) What is your OTA's output CM voltage?

almost 0v

>> Why is your output common-mode not 2.5 V? Why >> did you choose your output CM to be 0V? How can >> you get any output voltage swing if you choose your >> output common-mode to be 0V?
>> Why not make the output common-mode 2.5 V?

4) What are your power supplies?
vss:0v
vdd:5v

5) What range of "input signal" CM voltages do you want to tolerate?
0~5v

>> One important question is, why did you choose the >> flip-around gain-of-1 S/H architecture. Typically, this
>> architecture is used only if you really need LOW-
>> NOISE and HIGH-SPEED. However, it has definite
>> input
>> common-mode voltage restrictions. So, if you can
>> tolerate lower speeds and higher noise, but input
>> common-mode tolerance from 0-5V is important, you >> may want to consider using an architecture like in
>> Figure 12.41 page 432 of Dr. Razavi's book.

Sid

Title: Re: unit gain buffer problem
Post by capri on Apr 20^th, 2005, 9:15pm

sorry, I made a mistake, the cm output voltage is 2.5v.
The reason I want to apply this architecture is because I want to design a buffer interfacing the DAC to loads, the output range of DAC is from gnd to vdd. I need a high resolution and high speed buffer to sample the voltage and drive the load. Is there any other architectures can realize it? thank you.

Title: Re: unit gain buffer problem
Post by Sid on Apr 20^th, 2005, 9:49pm

What is the resolution of your DAC and what is its speed?

I am not a DAC expert and hence do not know much about your specific design interface. However, assuming your DAC is high-resolution, the design of the unity-gain buffer is non-trivial. Of the top of my head I am not sure if a switched-capacitor buffer is what you need. If your DAC output is continuous time, you may need a continuous time buffer, which is if anything even tougher to design for high-resolutions.

Let me know your DAC's speed and resolution. I will see if I can suggest something.

Sid

Sid

Title: Re: unit gain buffer problem
Post by capri on Apr 21^st, 2005, 12:28am

hi sid,
the dac is 10bit and it is not continuous time.
The settling time of buffer should less than 60us.
thx.

Title: Re: unit gain buffer problem
Post by Sid on Apr 21^st, 2005, 6:51am

You may want to try using the 2-capacitor unity gain S/H architecture in Figure 12.41 page 432 of Dr. Razavi's book. It is quite insensitive to input signal CM variations. However, if you want to go from 0 V to 5 V you may still have some issues. You need to try it out, I cannot say much more from here.

Best of luck,
Sid

Title: Re: unit gain buffer problem
Post by capri on Apr 21^st, 2005, 6:19pm

thank you sid.