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Design >> Mixed-Signal Design >> Undersampling in pipeline ADCs
https://designers-guide.org/forum/YaBB.pl?num=1113934527

Message started by Sid on Apr 19^th, 2005, 11:15am

Title: Undersampling in pipeline ADCs
Post by Sid on Apr 19^th, 2005, 11:15am

Hi,

My understanding is that the front-end sample-and-hold alone determines if an ADC can undersample with high-performance (assuming the clock jitter is somehow made low-enough).

Assuming a traditional gain-of-1 flip-around kind of S/H, I beleive, the ability to sample a very high-frequency input signal depends ONLY on the sampling switch linearity and input sampling bandwidth. By input sampling bandwidth, I mean w3dB = 1/RC, R = sampling switch resistance and C = sampling capacitor. Is this understanding correct?

Suppose I have a very high-linearity bootstrapped switch to sample the high-frequncy input signal, my 10 MS/s 12-bit ADC should be able to sample and quantize a 100 MHz signal (provided my bootstrapped switch and sampling capacitor can handle a 100 MHz signal with high-linearity and have a large enough BW). Is this correct?

In other words, do I need to worry about the performance of the OTA in the input S/H amplifier for undersampling performance or is it ONLY the boostrapped sampling switch that determines undersampling performance?

Any inputs will be appreciated.

Thanks,
Sid

Title: Re: Undersampling in pipeline ADCs
Post by ywguo on Apr 20^th, 2005, 10:16pm

Hi, Sid,

I agree with you. The undersampling performance is determined by its full power analog input bandwidth. You should optimize the the input capacitance and the on-resistance and linearity of the input switch.

Best regards,
Yawei

Title: Re: Undersampling in pipeline ADCs
Post by sheldon on Jun 1^st, 2005, 11:33pm

Sid,

One other thought, in your S/H are you assuming that the
OTA input is a virtual ground? In that case, doesn't the
bandwidth of the OTA become an issue, since you are
relying on the OTA to maintain the virtual ground?

Best Regards,

Art Schaldenbrand

Title: Re: Undersampling in pipeline ADCs
Post by Sid on Jun 2^nd, 2005, 7:39am

Hi Sheldon,

In a typical switched-capacitor sample-and-hold employing an OTA, the input AC signal never "reaches" the OTA. A typical example can be found in Andrew M. Abo's JSSC paper.

During phase 1, the input signal is sampled onto a capacitor through a MOS switch. At this point the OTA is idle with it's inputs typically shorted together and pulled down to an "ac ground". During phase 2, this sampled input voltage (currently stored on the sampling capacitor) is applied to the OTA's input terminal. Hence the OTA only sees a "sampled DC signal".

This is why I felt that for sampling a very high frequency input signal only the sampling switch and sampling capacitor need to be optimized and the OTA by itself need not have a large input bandwidth.

Please respond with any comments you may have.

-Sid

Title: Re: Undersampling in pipeline ADCs
Post by Paul on Jun 2^nd, 2005, 1:28pm

Hi Sid,

I may be wrong, but I agree with Art. During the second (hold) phase, the charge on the sampling capacitor (what you call a "sampled DC signal") is applied to the OTA. This means that the OTA output must adapt to this new input. The settling of the OTA output will take a given number of time constants, where the number depends on the desired resolution and the time constant is related to the OTA bandwidth.

Unless you give much more time to the OTA for settling than what you used for sampling, the OTA bandwidth will affect the performance of the S/H. But you may be partially correct in the following sense:
the hold phase must be long enough to provide full settling according to the desired resolution
the sampling phase must have a much more precise timing because the exact instant of opening the sampling switch is critical. That's also why clock jitter is such a critical factor.

I would be interested in learning more about the reasons to neglect OTA performance.

Paul

Title: Re: Undersampling in pipeline ADCs
Post by Sid on Jun 20^th, 2005, 10:14am

Hi Paul,

Sorry for the delayed response. I actually typed a long reply some time ago, but just as I was about to post it my Windows crashed!!!! Now, I will do it again and if you get this message then Windows did good!

I think our difference lies in coupling S/H sampling rate (i.e. fs) with input signal frequency (fin). Let us assume we need 12 bit precision (about 0.01% settling) and fs is 100 MHz (so T = 10 ns and T/2 = 5 ns). T/2 or 5 ns is the time the S/H output has to settle to within 0.01%.

Now, as you rightly say, OTA BW (i.e. fT) and feedback factor (beta) will determine if my OTA can acheive this specification. Assuming a "flip around" S/H, beta = 1 and so:
open-loop OTA fT = closed-loop f-3dB = 1/TAU.

We also need about 80 dB open loop OTA DC gain to satisfy 12-bit linearity and low gain-error. Let us assume we go ahead and realize this OTA.

My question now is: Can this S/H sample a 110 MHz input signal (at its maximum sampling rate of 100 MHz)? At this point is when I think the OTA does not matter. If my "passive-sampling" network (consisting of a MOS switch and a capacitor) can have high-enough bandwidth and high-enough linearity to sample a 110 MHz signal with 12-b precision - we should be all set!

This will be useful for software radio kind of applications where directly sampling a high-freq signal using a T/H and downconverting using an ADC will be attractive.

Do you agree? Please respond with any comments as I am not sure I am totally correct.

Thanks,
-Sid

Title: Re: Undersampling in pipeline ADCs
Post by Paul on Jun 22^nd, 2005, 1:58pm

Sid,

first I want to make clear that the signal you want to sample is located around 110MHz, but its BW is much lower. Correct? Otherwise you will experience folding.

Regarding the OTA BW, I am still convinced that it must comply to the settling specs. What is not clear to me is that in the latest post, you describe the specs you need for this and then you mention "I think the OTA does not matter"... Do you mean it doesn't matter as long as it complies to your specs mentioned above, or it doesn't matter at all. I agree with the first, not with the second. If you believe in the second, just go ahead and simulate your SH with a lousy 1MHz BW macromodel OTA and you should experience some bad surprises in the hold phase.

Paul

Title: Re: Undersampling in pipeline ADCs
Post by ywguo on Jun 23^rd, 2005, 12:01am

Hi,

I think Sid's message is clear now.

The OTA bandwidth determine the settling precision in a given settling time. But in undersampling application, the passive sampling network composed of switches and sampling capacitors determine the maximum analog input frequency. Those two points are independent each other.

Best regards,
Yawei

Title: Re: Undersampling in pipeline ADCs
Post by Paul on Jun 23^rd, 2005, 1:13am

Yawei,

in fact Sid's message was not totally clear to me, but yours makes it clear. I agree that the OTA BW is only related to fs and settling accuracy, while the analog input frequency is related to the sampling part.

But I am still a little confused when Sid talks about a 110MHz signal, which in my understanding represents the "center frequency" or something comparable, not the signal BW. Or am I still missing something.

Paul

Title: Re: Undersampling in pipeline ADCs
Post by Sid on Jun 23^rd, 2005, 4:01pm

Hi Paul,

The 110 MHz was just me picking a "high-frequency"! Yes, one would use a bandpass filter and restrict the bandwidth to under 50 MHz (i.e. BW < fsample/2 --> BW < 100/2, for 100 MS/s sampling). So, for example one would restrict the input signal from 85 MHz - to - 135 MHz (assuming an ideal brick wall anti-aliasing filter).

So, as Yawei clarified, I did mean that the OTA only affects settling time and settling precision (i.e. fsample and resolution). So OTA is critical for these two, but does not (directly) affect the maximum input frequency that can be sampled.

The sampling switch and the sampling capacitor alone directly affect the maximum input frequency that can be sampled.

Hope this is clearer...

Regards,
-Sid

Title: Re: Undersampling in pipeline ADCs
Post by sheldon on Jun 23^rd, 2005, 8:13pm

Sid, et al,

My bad earlier, I was thinking of the unity gain sampler, page 245
Razavi, when you were discussing tthe flip-around S/H. The S/H by
Yang, "A 3V 340mW 14bit 75MS/s CMOS ADC with 85dB SFDR
at Nyquist Input". Yang's S/H does have very high bandwidth and
is appropriate for undersampling. Other than the usual issues for the
OTA, you need to make sure the input common-mode rejection is
high.

Best Regards,

Scheldon