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Design >> Analog Design >> Automating the Simulation Process.
https://designers-guide.org/forum/YaBB.pl?num=1115222066

Message started by kamesh419 on May 4^th, 2005, 8:54am

Title: Automating the Simulation Process.
Post by kamesh419 on May 4^th, 2005, 8:54am

Dear all,

I have a model. The Model is shown in the following link below.

http://www.aisl.cyd.liu.se/temp/image.jpg

It has an
1) 8-bit Adder
2) a Verilog-A Module
3) Some VPWLF Sources which take "files" as inputs.

Some Facts:
1) I have to simulate it for 8, 12 and 16 bit adders. Not only that I need to Simulate the whole Model with an Adder (8,12 and 16 bits) but also I have to simulate it for Multiplier and Divider (both 8, 12 and 16 bits) as well. So now the number of cases for me would be like 9 or probably more if I intend to do the combinations of Adders, Multipliers and Dividers.
2) The number of VPWLF sources also change accordingly and so does the Verilog-A modules.

What I want to Do:
1) Simulate my Model shown in the picture (using spectre) and as explained above (The number of such models that I need to simulate will be 9 or more). So the Number of VPWLF sources changes with every simulation so does the Verilog-A module. So I strongly believe that I need to automate this process of Simulation. Since doing this manually would be a tedious task. I am looking for suggestions from you in what way I can go about doing this automation.

I have some Idea that the Automation has to be done using Ocean Scripting language and SKILL. But not sure exactly how I can go about doing this. Can any one suggest me in the right direction.

Thanks in advance,
Kamesh.