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Design Languages >> Verilog-AMS >> Hidden state in VCO
https://designers-guide.org/forum/YaBB.pl?num=1116862555

Message started by tromeros on May 23^rd, 2005, 8:35am

Title: Hidden state in VCO
Post by tromeros on May 23^rd, 2005, 8:35am

Hi to all, this is my first post and I am very glad to participate in such an interesting and useful forum.
I have a question concerning the VCO described in the paper "Predicting the phase noise and jitter of PLL Based frequency synthesizers". In page 37 there is the verilog code of a VCO. I wrote this code in Cadence and had a transient analysis. However, when I try to make a pss analysis I get the error that there is a hidden state, concerning the variable dT. I read the paper "Hidden state in SpectreRF" but I cannot correct the problem. I wonder if it is possible to have pss analysis in the specific behanioral model. Thanks in advance. :)

Title: Re: Hidden state in VCO
Post by Ken Kundert on May 23^rd, 2005, 10:43pm

Hidden state is not the only reason why that model will not run in PSS. The model exhibits jitter, and so does not produce a periodic output. As such, any circuit containing this VCO cannot achieve a periodic steady state.

If you remove the jitter code, the model should work in PSS.

-Ken