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Design Languages >> Verilog-AMS >> Does the Netlist include the Verilog-A?
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Message started by kamesh419 on May 25^th, 2005, 9:59am

Title: Does the Netlist include the Verilog-A?
Post by kamesh419 on May 25^th, 2005, 9:59am

Dear all,

I have a design (Adder block + VerilogA block). When I try to simulate my design with spectre it produces a netlist file called "netlist" and 2 other files called "netlistHeader" and "netlistFooter". What I was wondering about is does the "netlist" include my full design (that is Adder block + VerilogA block) or it only includes my Adder block. and I have to do a "cat command" to get my final netlist.

when i have checked my "netlistFooter" file it has ahdl_include to my VerilogA file.

Thanks and Regards,
Kamesh.

Title: Re: Does the Netlist include the Verilog-A?
Post by Andrew Beckett on May 25^th, 2005, 10:09pm

The analog design environment produces a netlist for the design part (in the file netlist), and then puts things like includes for model files, includes of ahdl etc in the netlistFooter and netlistHeader files. It also writes out the analyses into a file called .controlStatements - there are a bunch of other dot files that it writes.

Anyway, these are all assembled into the input.scs file - which is what is simulated. So you shouldn't have to cat them - it does this for you.

The reason it does this is because these things are done incrementally to save time - no point in renetlisting the design if nothing changed.

Regards,

Andrew.