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Design >> Analog Design >> Test Bench for Differential Circuit by Ken Kundert
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Message started by Leyman on May 31^st, 2005, 5:32pm

Title: Test Bench for Differential Circuit by Ken Kundert
Post by Leyman on May 31^st, 2005, 5:32pm

Hi teachers,

I am new in Analog IC Design. I want to simulate frequency response of a fully differential OTA using 'A Test Bench for Differential Circuit by Kenneth S. Kundert. (The paper can be download from www.designers-guide.com).

When implementing a test bench, I follow exactly what have been written in the paper. I set Vdm=1V ac, Vcm=0V, Rid=Ric=Rod=Roc=0 ohm. Run ac analysis and probe differential output at node d.

The result is a bit strange for me. The phase response curve looks fine but the gain response curve is somehow funny. It looks like a response for high pass filter.( Gain increase linearly until it reaches certain level at certain frequency the gain become constant)

Anyone can tell me why is this happening? Is it something wrong with my setup? How about the setup for settling time and other related quantities?

thanks

Title: Re: Test Bench for Differential Circuit by Ken Kun
Post by Ken Kundert on Jun 1^st, 2005, 8:19am

Without seeing the netlist and the results it is unlikely that we would be able to identify what is going wrong. I recommend that you try to debug your circuit by tracing the signal through the circuit. For example, you can start by assuring that the input signal makes it through the input balun to the inputs of your amplifier and looks like a differential signal. Then trace the signal through your circuit. Does it make it to the output? Is it differential at the output? Does the differential output signal make it through the output balun do appear at the d output as you would expect. Etc.

-Ken

Title: Re: Test Bench for Differential Circuit by Ken Kun
Post by Frank Wiedmann on Jun 1^st, 2005, 11:27pm

My personal guess would be that the operating point of the circuit is not correct. Maybe a different value should be chosen for Vcm. The highpass characteristic might be due to capacitive coupling from the gates of the input transistors which are not in their active region.