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Design >> Analog Design >> Settling Time and Slew Rate Mesurement
https://designers-guide.org/forum/YaBB.pl?num=1117797472

Message started by Packiaraj.V. on Jun 3^rd, 2005, 4:17am

Title: Settling Time and Slew Rate Mesurement
Post by Packiaraj.V. on Jun 3^rd, 2005, 4:17am

Hi,
Can any one tell me the procedure for measuring slew rate and settling time for fully differential OTA.
I followed the paper " A Fast settling OTA with 90 db gain for SC circuits" by BULT and GEELAN., which discusses that procudure for single ended OTA. I modified that for fully differential OTA. I connected equal value of capacitances and resistances to the input and feedback sides. Though my Non Slewing class AB OTA had gain of 75 dB and UGF of 500 MHz in typical corner, the settling time it displayed was 20 ns. I doubt whether my procedure is correct. Help me.
And while doing settling time measurement should the DC shift for the step voltage be zero or input CM voltage needed to bias OTA?
I would be grateful if any one suggest good material for this.
Thanx,
Packiaraj.V.

Title: Re: Settling Time and Slew Rate Mesurement
Post by Leyman on Jun 7^th, 2005, 7:10pm

Hi Packiaraj. V,

I recommend you read Stanford lecture notes on Analog Circuit Design. They provide some usefull informations about test benches for simulating loop gain, settling time, step response etc.

go to the following link:
http://www.stanford.edu/class/ee214/handouts/

I hope it helps..good luck! :)

-leyman-

Title: Re: Settling Time and Slew Rate Mesurement
Post by Paul on Jun 10^th, 2005, 8:41am

Hello Packiaraj,

the settling time is related to the UGF through the settling error you can tolerate. Your specifications should define that error and the settling time, from which you can then calculate the required UGF. It is difficult to judge if your results are correct without knowing your target settling error, but the values you mention sound reasonable to me.

Paul