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Other CAD Tools >> Physical Verification, Extraction and Analysis >> problems suffered during LVS
https://designers-guide.org/forum/YaBB.pl?num=1118386966

Message started by Robert on Jun 10^th, 2005, 12:02am

Title: problems suffered during LVS
Post by Robert on Jun 10^th, 2005, 12:02am

hi,guys
our company used the charter 0.35um RF CMOS process, and get the PDK and pcells from Cadence. now, when we serie or parallel resistors in the schematic, then do the same way in layout, extracted, run LVS, it comes out some error:"combined device:Err:Sch Res missing params: l ; lay Res missing params: l
anyguys can tell me why would suffer this problem and how to solve it.

Title: Re: problems suffered during LVS
Post by Alef on Apr 12^th, 2006, 6:41am

The first reason of this error may be the absense of parameter "l" in device's CDF ->Simulation information -> auLvs. Also your extract.rul may has not nameParameter("l") for this device (but schematic netlist in this case has parameter l for your device). I think? the first reason is the most possible.