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Design >> High-Power Design >> Large Signal Stability for DC/DC Buck
https://designers-guide.org/forum/YaBB.pl?num=1118538452

Message started by richard88 on Jun 11^th, 2005, 6:07pm

Title: Large Signal Stability for DC/DC Buck
Post by richard88 on Jun 11^th, 2005, 6:07pm

It is stated that the large signal stability condition is satisfied if the rising slope of the ramp is higher than the rising slope of the voltage ripple just before the comparator.
I wonder if the above is not satisfied, are we able to see the oscillation in simulation ? assuming we are using cadence spice tool.
Thanks !

Title: Re: Large Signal Stability for DC/DC Buck
Post by Eugene on Jul 7^th, 2005, 10:13am

It sounds like you are describing what we used to call the subharmonic oscillation in current mode converters. The comparator inputs are (1) a signal related to the inductor current and (2) an error signal with a stabilization ramp riding on it. If you are indeed referring to the current mode subharmonic oscillation, I believe you can simulate it, especially if you are simulating start up transients.

Title: Re: Large Signal Stability for DC/DC Buck
Post by richard88 on Jul 12^th, 2005, 5:42am

Eugene,
It looked very similar to the subharmonic oscillation as in the current mode converter.
But when I asked someone senior in my company about voltage mode converter, the oscillation due to the higher gain of error amp and output slope (compare to the ramp signal), is more of theory and is rarely seen.
However, I get to read about it in many articles (design articles), which would not dig too much about it, but seems like a requirement in the design procedures.

Thanks.