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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Simulate "thd" of a sample and hold https://designers-guide.org/forum/YaBB.pl?num=1118555245 Message started by ericjohnson on Jun 11th, 2005, 10:47pm |
Title: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 11th, 2005, 10:47pm Greetings, How to simulate the "thd" performance of a sample and hold block? when doing the dft, should we directly take SHA's output waveform (for cadence Analog Artist enviroment)? Thank you! Eric |
Title: Re: Simulate "thd" of a sample and hold Post by Andrew Beckett on Jun 12th, 2005, 12:23pm You could do that (make sure that you set strobeperiod on the transient analysis to coincide with your sampling instant to remove the interpolation error in the dft sampling). Or you could use PSS or QPSS to get this directly, I guess. Regards, Andrew. |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 12th, 2005, 3:00pm Can you please give more details? My simulation result seems to be not reasonable. For a simple MOSFET + Cap type sample and hold, the thd is about 15%...... Thank you! Andrew Beckett wrote on Jun 12th, 2005, 12:23pm:
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Title: Re: Simulate "thd" of a sample and hold Post by sheldon on Jun 12th, 2005, 7:47pm ericjohnson, To strobe the output use the Spectre tran command, skipstart, to define the point where you would like to start the data record for the FFT and use, strobeperiod, to set the fixed time for the FFT. For example, assuming you have a 10MHz clock and would like to allow 10 periods for the start-up transients to settle, tranAna tran .... skipstart=1.098u strobeperiod=100n Remeber: that you allowed 10 periods to settle transients, 1u, and you need the S/H to acquire, switch into hold mode, and settle, 98ns. The other options are to use the zvcvs components and or the zvcvs component with the fourier component. The zvcvs acts like an ideal sample and hold. By performing the FFT on the output of the zvcvs, you can get very accurate results. BTW, I use the zvcvs. The setup of the zvcvs is similar to the setup of the strobe. Best Regards, Sheldon |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 12th, 2005, 8:35pm Thank you so much, Sheldon! But I'm still not sure if I understood you correctly. Here's what I did before using Cadence Analog Design enviroment(Artist) (basically tried to follow the Cadence manual) 1. Input: 10M Sine wave Sampling Clock: 100M 2. Choose "tran" analysis, set stop time 10 1005n (a slightly longer than 100 clock cycles (10 input signal cycles). 3. Click "Options" in the popup "choosing Analyses" window, set step to "10n" 4. Run simulation 5. plot Vin and Vout 6. Use Calculator, choose Vout waveform 7. Use thd function, set start 0, end 1000n. Could you please comment on this ADE/calculator based method? Thanks! sheldon wrote on Jun 12th, 2005, 7:47pm:
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Title: Re: Simulate "thd" of a sample and hold Post by sheldon on Jun 12th, 2005, 9:17pm Ericjohnson, First, don't use 10MHz, selecting the input frequency requires a lot of care. Next, the number of samples needs to be a power of 2, if you use standard FFTs. So to setup your simulation, assume 128 point FFT and use input frequency of 10.156250MHz( 13/128 ), 10 clock cycles to settle the start up transients, 100ns, and that the output is valid at 9.8ns into the clock cycle. tranAna tran stop=1.4u skipstart=109.8n strobeperiod=10n In the calculator, after selecting the waveform, vt --> V(out)[exact syntax may be different] Then select dft from 109.8n to 1.3898u number of points 128 you can use the rectangular window. Don't forget to convert to dB20 before plotting. The alternative, you can sample the output node with a zvcvs source sampler zvcvs sampled 0 out 0 td=109.8n ts=10n and then 1) perform an FFT on the output, see above 2)use Spectre's fourier analysis fourAna sampled 0 fourier fund=10.156250M harms=64 normharms=13 where=logfile order=2 Best Regards, Sheldon |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 12th, 2005, 11:22pm Millions of thanks! Just did a quick test following your instruction. The results looks reasonable. Please forgive my ignorance. Could you explain why selecting the input frequency requires a lot of care? I understand the samples have to be a power of 2 (for FFT calculation purpose). But where does 13 come from? I also don't understand the part: 10 clock cycles to settle the start up transients, 100ns, and that the output is valid at 9.8ns into the clock cycle. 1)Why wait 10 cycles? 2) Why pick 9.8n? 3) I noticed you start from 109.8n to 1.3898u for the DFT. It's 1280ns. That's 128 points per 10ns. Could you give more insignt of this? Thank you and Best regards, Eric |
Title: Re: Simulate "thd" of a sample and hold Post by sheldon on Jun 13th, 2005, 6:14am Eric, First, comment we are simulating not measuring performance on a test bench so we are taking advantage of the simulator's "ideality" to make the analysis better. Some general guidelines for a well-behaved FFT of s/h and ADCs are(See Ken's book for more details): 1) The data record for the FFT should include an integer number of evenly spaced(in time) data points. --> This can be a issue, which is one of the reasons why Spectre uses the Fourier integral 2) The data record should have an integer number of cycles of the input and the sample periods. --> This avoids needing to use window functions., that is, there is no spectral leakage so windowing is not required. 3) The ratio of the input frequency to the sample frequency should be a prime number. --> For ADCs in particular, if the input frequency is a related to the sample frequency, fin=10MHz and fs=100MHz. Then only certain codes get exercised and the spectrum has discrete tones at the harmonic frequencies: 10MHz, 20MHz, .. While the SNR calculation is correct, the SFDR and THD calculations are not. All the quantatization noise ends up in the harmonics. 4) The 10 periods is a WAG. Transient analysis takes a while to settle the startup transient. If you think about PSS, the shooting algorithm eliminates the transient start-up and directly calculates the steady-state. In this case, we allowed 10 periods for the circuit to reach "sinusiodal steady-state". In complex designs, circuits can sometimes require long times to settle startup transients. 5) The 9.8ns is a WAG. Assuming that 5ns is allowed for sampling and 5ns are allowed to settle the hold step, then the hold step should be "settled" at about 4.8ns after the start of the hold period. If you wait to long, then the S/H starts to switch back into sample mode and the result is not valid. Since simulators tend to anticipate transistions, you need to allow a little margin. 6) Given your targets of fin=10MHz and fs=100MHz, and your (anticipated) desire for a "reasonable" simulation time. The selections were: a) 128 points for the FFT, power of 2, with reasonable accuracy. Increasing the number of points doubles the simulation and lowers the noise floor. Increasing number of points in the FFT reduces the "resolution bandwidth" of the bin, i.e., less rt Hz, less bandwidth less noise b) Your target input frequency is 10MHz so 13 is a prime number that results in an input tone that is close to your target. Hope this helps! Best Regards, Sheldon |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 13th, 2005, 7:50am Wow, thank you so much for spending your valuable time to give such a detailed explaination. Warmest regards, Eric |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 13th, 2005, 5:39pm sheldon, I was confused by the following questions: 1. After checking the clock plot, I noticed the clock holds at either high or low (i.e., not a pulse train anymore). Why is that? And why the SHA outputs follow the input sine wave with a little distortion/delay? I mean, since after the initial 10 clock cycles, the clock stays at high, then the outputs should hold at the last value the SHA sampled, right? 2. Why for other circuits, we don't wait for a while when using the transient analysis? Thanks again!!! |
Title: Re: Simulate "thd" of a sample and hold Post by sheldon on Jun 13th, 2005, 6:17pm Eric, First, using the strobe function is like using a strobe light, you only see circuit operation at an instant in time. When you use a timing light, you see the notch at top dead center, even though it is rotating(ya I'm a dinosaur). When you use skipstart, the output data is only saved at the time point that you strobe. Since you are "strobing" during the hold period, the clock will appear to always be in the hold mode. The ouput follows the input with a little distortion and delay because the switch and the sampling capacitor acts like an RC low-pass filter. This phenomena sets the "analog bandwidth" of the S/H and ADC. Best Regards, Sheldon |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 13th, 2005, 6:40pm Tons of thanks... But here comes the question again: from your description, this strobing function is sort of like an impulse sampling. However, we are trying to measure/simulate a pulse train sampling, which has different spectrum. Then seems to me the results obtained by strobing is not accurate... |
Title: Re: Simulate "thd" of a sample and hold Post by sheldon on Jun 13th, 2005, 6:50pm Eric, Maybe it would be better to think of strobing as an alternative method of time step control that controls the simulator time stepping so the simulator stops and simulates the circuit at exactly the time point required for the FFT. This eliminates interpolation error in the FFT and interpolation error can be a significant issue as FFT resolution increases. Best Regards, Sheldon |
Title: Re: Simulate "thd" of a sample and hold Post by ericjohnson on Jun 13th, 2005, 7:34pm First of all, thank sheldon for his patience and insightful answers! Here's a summary. Q - What's wrong with my original simulation setup? A - From your initial post, fin=10MHz and fs=100MHz, with simulation time of 1005s. 1) So the FFT has 100 data points, and this is not a power of 2. 2) The input and clock frequency are harmonically related, that is the clock is the 10th harmonic of the input, or only input states exist, so the quantitazation noise will show up in the harmonics of the input Q - "thd" function in calculator A - the THD function is not applicable to this problem, i.e., S/H and ADC THD calculation(it works only in special cases). The THD is intended for non-sampled circuits. In sampled-circuits the harmonics are "folded" back into the baseband. So the 6th harmonic appears at 40MHz, the 7th harmonic at 30MHz, ... For your current simulation this is not a big issue, but, sorry, you need to do the THD calculation manually. |
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