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Design Languages >> Verilog-AMS >> Aborting a simulation thru VerilogA
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Message started by Eugene on Jun 14^th, 2005, 11:08am

Title: Aborting a simulation thru VerilogA
Post by Eugene on Jun 14^th, 2005, 11:08am

Does anyone know of a clean VerilogA trick to deliberately halt a Spectre simulation? I would like Spectre to perform the DC, initial transient, or perhaps an AC analysis, check the results, and then abort the remaining analyses if the results fail a user-defined test. I do not want to wait for a long transient analysis only to find that the DC, initial transient, or even the AC analysis indicated a problem. For example, if the DC analysis converges but shows a bias is too low to generate meaningful transient results, I don't want a parametric sweep to waste a day on that data point. I'd rather abort the simulation and move on to the next data point in the sweep. Currently, I am driving a terminal current to 1e20 amps to deliberately crash the simulator under some conditions but that is somewhat clumsy and does not identify which of my tests failed.

Title: Re: Aborting a simulation thru VerilogA
Post by sheldon on Jun 14^th, 2005, 7:39pm

Eugene,

Have you looked at SpectreMDL? It was created for
the task of perofrming measurements can control
the simulator.

Best Regards,

Sheldon

Title: Re: Aborting a simulation thru VerilogA
Post by Andrew Beckett on Jun 14^th, 2005, 9:02pm

There's an enhancement request for doing this:

PCR: 755453
Title: Need a way to prematurely terminate an analysis

There currently is an internal task for doing this, but it's not public as it's quite likely to change (it's not part of the LRM).

Regards,

Andrew.

Title: Re: Aborting a simulation thru VerilogA
Post by Eugene on Jun 15^th, 2005, 10:20am

Thanks Sheldon and Andrew for you comments. I will check out SpectreMDL.

Title: Re: Aborting a simulation thru VerilogA
Post by John O Donovan on Jun 16^th, 2005, 1:58pm

Hi,

SpectreMDL probably won't help you either. It cannot really
alter the control flow as you wish here. It can stop a specific
transient prematurely when all measurements are complete
for that analysis, but you cannot conditionally run another
analysis based upon the result of a prior analysis, (ignoring
a search/optimization type loop).

Other than using Verilog-A, maybe the cleanest approach
would be to use the 'assert' statement to create your tests.
Then if the assert fails, it could exit without running any more
analyses. In the following example, you can define a
set of asserts, which generate an error upon failure. These
are then disabled for the following transient analysis. If
the assert(s) fail, the dc analysis will error out and then the
transient will not run. If they succeed, the transient will run
as expected.


// Define you assertions
assert1 assert dev=v1 param=i min=-25m level=error
// Run the DC
dc1 dc
// Disable the asserts for the transient analysis.
disableasserts checklimit disable=[ "assert1" ]
tran1 tran stop=1u

Best Regards,
John

Title: Re: Aborting a simulation thru VerilogA
Post by sheldon on Jun 16^th, 2005, 5:17pm

Eugene,

Since you are writing a Verilog-A model anyway, wouldn't
writing an OCEAN script file be easier? Since the transient
analysis does not need to be run with the dc and ac
analysis. Why not do two runs, for example, you might run
the dc and ac analysis, do the measurements, then
generate a file to run the transient analysis. It would not
be entirely automatic but it would give you insight into
the transient analysis run time before the simulation
starts.

Never created runs files from an OCEAN script, but I have
written OCEAN scripts that automatically generate data
sheets, the principle is the same.

Best Regards,

Sheldon

Title: Re: Aborting a simulation thru VerilogA
Post by Eugene on Jun 16^th, 2005, 11:01pm

John,
Thanks for the code. I will check it out.

Sheldon,
Thanks for the Ocean suggestion. However, my brief experience with Ocean is that it is fairly cryptic. Nevertheless, it may be time to check Ocean out too.

Thanks again guys.

Title: Re: Aborting a simulation thru VerilogA
Post by Eugene on Jun 17^th, 2005, 6:50pm

In looking through the Cadence on-line documentation for something else I stumbled across the $finish command. I tried it and it appears to do exactly what I want.

There is also a $stop function that lets you resume simulation.

OOPs! It seems I jumped the gun. The $finish works for one run but not with the Parametric Tool. If I sweep a parameter that should invoke the $finish statement on the first run, all subsequent parametric runs terminate too, even if a single separate run at those parameter values runs successfully. Guess I'll try MDL or Ocean.

Title: Re: Aborting a simulation thru VerilogA
Post by Andrew Beckett on Jun 17^th, 2005, 11:14pm

Hi Eugene,

Yes, it ($stop, $finish) completely kills the simulator at the moment. We have a PCR on this to either fix that, or provide an alternative function to finish just that analysis ;)

Regards,

Andrew.

Title: Re: Aborting a simulation thru VerilogA
Post by manyoki on Oct 14^th, 2005, 2:39pm

i used $stop successfully during parametric sweeps to cut down sim time once a condition was satisfied.

for example, the following simple code makes the simulator stop the current run when sigp-sign has a positive zero crossing:

`include "discipline.h"
`include "constants.h"

module stopflag(sigp,sign);
input sigp, sign;
electrical sigp, sign;

analog begin
@ (cross( V(sigp) - V(sign), +1 ))
$stop;
end
endmodule