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Design >> Mixed-Signal Design >> sigma-delta adc
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Message started by savitha on Jun 19^th, 2005, 11:38pm

Title: sigma-delta adc
Post by savitha on Jun 19^th, 2005, 11:38pm

Hi all,

while deciding the order of the sigma delta modulator for adc, which all parameters i need to consider.

regards,
savitha

Title: Re: sigma-delta adc
Post by Paul on Jun 22^nd, 2005, 2:01pm

Savitha,

I believe you can find a detailed discussion of the major sigma-delta ADC parameters in many graduate-level data converter text books, like Temes, Norsworthy, Schreier and Razavi.

Paul

Title: Re: sigma-delta adc
Post by savitha on Jun 22^nd, 2005, 9:33pm

Hi Paul,

currently i am referring Razavi text book, ok i will go through other text books which you have mentioned. thanks for the suggestion.

Regards,
Savitha

Title: Re: sigma-delta adc
Post by maxam on Jul 25^th, 2005, 10:39pm

For high order DSM, the most concern is the stability

Title: Re: sigma-delta adc
Post by carl on Sep 6^th, 2005, 8:44pm

you can use the MATLAB SDToolbox to generate the loop parameters, you can download it from www.mathworks.com/matlabcentral/fileexchange

Title: Re: sigma-delta adc
Post by Ken Kundert on Sep 6^th, 2005, 10:17pm

I was just doing a little reading on this topic. What I found was:
1. To get better resolution you can either increase the oversampling ratio, increase the order of the converter, or increase the number of levels produced by the quantizer.
2. If you also want to handle high bandwidth signals, it is difficult to increase the oversampling ratio, so you are limited to the other two approaches.
3. Using a simple delta-sigma converter, the risk of instability upon saturation increases as the order of the converter increases beyond 2. Using an order greater than 4 is rare.
4. You can effectively create higher-order converters using MASH type architectures, which combine a series of lower-order converters together in such a way as to provide the accuracy benefits of high order without the risk of instability.
5. MASH architectures require careful matching between the stages which is only possible with conventional (discrete-time or switched-capacitor) converters (in these types of converters, only capacitor matching is important).
6. In particular, the matching in continuous-time converters involves both resistors and capacitors, and so is much inferior to capacitor matching alone. As such, continuous-time converters are not suitable for use in MASH architectures. For these converters, the best way to increase accuracy is to increase the number of levels in the quantizer.

-Ken

Title: Re: sigma-delta adc
Post by Paul on Sep 7^th, 2005, 12:56pm

Savitha,

in fact you forgot to mention whether you were concerned about A/D conversion or D/A conversion. I guessed you were talking about ADCs, but maybe you can confirm this...

And as an addition to Ken's quite complete overview, I wanted to note that:
- continuous-time ADCs are sensitive to clock jitter, which may be critical at high sampling rates.
- multi-bit quantizers require mismatch-shaping (MMS) algorithms to keep the non-linearity low. Unfortunately MMS is not efficient at low OSR, which means that for RF ADCs, both the multi-bit approach and the high OSR approach are not very suitable. In that case, high-order single-bit topologies may be used, but are quite tricky to design due to the stability issues mentioned by Ken.
An empirical study of high-order single-bit delta-sigma modulators
Schreier, R., IEEE Transactions on Circuits and Systems II, Vol.40, Aug. 1993.

Paul

Title: Re: sigma-delta adc
Post by savitha on Sep 7^th, 2005, 10:13pm

Hi Paul,

You are right, i am designing a 4 bit delta-sigma ADC.

Regards,
Savitha

Title: Re: sigma-delta adc
Post by vivkr on Sep 15^th, 2005, 1:10am

Hi Paul,

You are not quite right about the jitter sensitivity of CT delta-sigma ADCs. While the standard textbook model of this ADC is highly sensitive to clock jitter in the DAC feedback, this problem can be virtually eliminated using a simple and elegant solution.

Instead of feeding in a fixed current via the DAC feedback for a fixed amount of time (which implies large errors if this fixed-amount of time is not fixed but has jitter), you just connect a switched-capacitor which feeds in the same net charge that you would otherwise provide through the current.

Basically, dQ is the charge from the DAC feedback. You can realize it using

Ifb*dT or C.Vref. The former is timing-sensitive, the latter not.

Unfortunately, many people are not aware of this solution though it has been around for a very long while. I dont know the exact source of this solution, but you will find a description in the latest book by Schreier and Temes "Understanding Delta-Sigma Converters". Look in Chapter 6 on Implementation Issues.

Regards
Vivek

Title: Re: sigma-delta adc
Post by Paul on Sep 15^th, 2005, 7:53am

Vivek,

I did not have time yet to get the latest Schreier-Temes... I guess you will do this using two capacitors to feed the usually differential signal path with the reference charge and to minimize charge injection. Right? In that case, what about capacitor mismatch, in how far does it limit the performance of your design?

Second and probably more important point: CT modulators are interesting because the OTAs don't need a bandwidth as large as for a switched-cap implementation. I would imagine this doesn't hold any more for the discussed implementation, does it?

Thanks in advance for your comments on these issues.

Paul

Title: Re: sigma-delta adc
Post by vivkr on Sep 19^th, 2005, 3:19am

Hi Paul,

I think cap mismatch is not really such a big issue. First of all, mismatch will be present even in CT modulators when they are fully differential, and typically cap mismatch is not so severe as to limit performance. I would think that cap variation would merely change the modulator filter coefficients very slightly in a good design.

The second point you make is more relevant, and I had not thought of this since I had only read about this technique very briefly. However, the opamp bandwidth will probably have to be increased, thus giving away the basic advantage of using a CT modulator. So it is quite unusual that this scheme should be suggested in the text. Perhaps, the authors are aware of some simple workaround, or else they provide this scheme considering that it is usually easier to get higher bandwidth by burning more power than reducing the clock jitter to the levels demanded by a standard CT modulator.

Maybe someone can enlighten us on this point.

Regards
Vivek

Title: Re: sigma-delta adc
Post by sivashankar on Sep 20^th, 2005, 9:59pm

U have to C how many bit adc and accuracy of the ADC.
based on that u can decide delta ADC

Title: Re: sigma-delta adc
Post by Paul on Sep 21^st, 2005, 12:35am

Sivashankar,

I don't want to argue about your writing style, but I have to say I didn't understand anything... Would you mind changing your post to something more explicit?

Paul

PS: I though U was a voltage and C a capacitance for electrical engineers ;)