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Design >> Analog Design >> CMFB stability simulation?
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Message started by ericjohnson on Jun 21^st, 2005, 2:09pm

Title: CMFB stability simulation?
Post by ericjohnson on Jun 21^st, 2005, 2:09pm

Could anyone provide some insignts on CMFB block stability simulation? Should the GBW of CMFB be smaller than that of the main amplifier? Thank you!

Best regards,

Eric

Title: Re: CMFB stability simulation?
Post by sheldon on Jun 21^st, 2005, 9:01pm

Eric,

Probably not, the purpose of the CMFB is to maintain the common
mode level of the output signals. So it should probably have more
bandwidth and more slew rate the differential signal path. If the CMFB
is not faster, then common mode level is not maintained. Potentially,
there will be common mode rejection issue is subsequent stages and
worst case common mode range issues.

Sheldon

Title: Re: CMFB stability simulation?
Post by ericjohnson on Jun 21^st, 2005, 9:53pm

Thank you, Sheldon. That's also what I thought. But I remembered I saw an IEEE journal paper a while back that the authors claimed "...it's well known that CMFB should (?) have smaller bandwidth than the main amplifier...". That's where my confusing comes from.

My another guess is that CMFB may have poles closer to each other so it may be difficult to design it with wider bandwidth than the main amplifier?

Eric

Title: Re: CMFB stability simulation?
Post by sheldon on Jun 21^st, 2005, 10:30pm

Eric,

Took a quick look at Gray & Meyer, rev. 4, and it seems like there
is no perfect answer:
1) CMFB loops usually have more poles, so they need more compensation
and therefore have less bandwidth.
2) CMFB don't supress common-mode noise unless they have gain at
the frequency of the noise.

So the issue is that CMFB bandwidth is maybe good but difficult to
achieve in practice, that is, it adds power/area/...

Sheldon

Title: Re: CMFB stability simulation?
Post by blam on Jun 22^nd, 2005, 11:54am

Here is another argument why CMFB loop doesn't need high bandwidth.

The main amplifier needs high bandwidht beecuase it requires to settle to some accuracy, say 0.1% for a 10-bit ADC, within half a clock cycle. The output of CMFB loop is used to bias the tail current of the main amplifier. Within 2-5% of the desired value, this bias already makes the main amplier getting close to the desired common mode output voltage. The bandwidth required to settle to 5% of accuracy is less than to 0.1%.

Of course, one can design CMFB loop with higher bandwidth. But as pointed out, CMFB loop has more poles and the design of high bandwidth loop means high power.

-Bill

Title: Re: CMFB stability simulation?
Post by Paul on Jun 22^nd, 2005, 1:24pm

Funny thing, I stumbled over this in Laker & Sansen a couple of days ago. They mention that (I guess in the general case) the CM GBW must be larger than the DM GBW. I am puzzled by the statement Eric mentions and I cannot understand why the CM GBW _should_ be lower, but I believe the statement from L&S on the other hand is too general in many cases.

In an IC, the DM BW of each amplifier is defined by design (unlike a general purpose OP-AMP you can buy from the shelf). In this case, I believe a less stringent constraint relating closed-loop DM BW and CM GBW could be found, but I cannot make a definitive statement on this as I didn't have time yet to investigate further. This should ultimately correspond to Bill's point of view that a very accurate settling is not needed in the CM path.

Of course I agree with everybody about the number of poles making the above mentioned conditions difficult to reach.

Paul