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Design >> Analog Design >> help! charge pump layout
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Message started by nus_lin on Jun 27^th, 2005, 4:14am

Title: help! charge pump layout
Post by nus_lin on Jun 27^th, 2005, 4:14am

one of my building block is to provide high voltage (say: 2Vdd or 3Vdd) to a MEMS electrostatic actuator, so I am thinking of using voltage tripper.

The topology is a very traditional and uses cross-connected mosfet and commuting clocks. But I need more information for the layout to continue. I am not sure about how to avoid possible latch-up problem.

This voltage tripper draws almost no current so it is a pure capacitive load. My Vdd is 3.3V, so for the first stage which pumps to 2*Vdd I planed to use normal nmos transistor because the process file said that breakdown voltage for ndiff diode is 9V typical. And for the next stage which pumps the voltage from 2Vdd to 3Vdd, I planned to use nmosh transistor, which is limited by the nwell-sub junction breakdown voltage. Am I right?

Another question is that the nmosh layout drawn by myself can not pass the DRC check because ndiff can not cross nwell by design rule, how did you solve this problem?

Is there any layout example available?

Thank you very much.