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Modeling >> Semiconductor Devices >> scalible varactor model
https://designers-guide.org/forum/YaBB.pl?num=1121233781

Message started by kimsm on Jul 12^th, 2005, 10:49pm

Title: scalible varactor model
Post by kimsm on Jul 12^th, 2005, 10:49pm

I have some question about spectre format.

I want conversion of hspice format sub-circuit into spectre format sub-circuit.

.LIB LVAR_CAP
*
.subckt lvar_cap in out w=1 l=1 nf=1
.param area='l*w' peri='(2*l+2*w)' pt='temper'
+ tc1aa=-1.7089E-4 tc1ab=-4.2154E-5 tc1ac= 3.8616E-3 tc1ad= 1.7499E-3
+ tc2aa= 3.692E-7 tc2ab=-3.553E-8 tc2ac= 6.1988E-7 tc2ad=-7.774E-7
+ tc1pa= 7.8389E-5 tc1pb= 1.4114E-4 tc1pc= 1.0051E-3 tc1pd= 3.9153E-3
+ tc2pa= 6.6065E-7 tc2pb=-4.2438E-7 tc2pc=-1.4547E-5 tc2pd=-8.3602E-7
+ cgmin_va= 1.8247E-3 dcg_va= 5.0975E-3
+ dvg0_va=-0.03757 vgnorm_va= 0.28668
+ cgmin_vp= 1.6237E-10 dcg_vp=-8.8928E-11
+ dvg0_vp= 0.04955 vgnorm_vp= 0.21354
+ cgmina='cgmin_va*(1+tc1aa*(pt-25)+tc2aa*(pt-25)*(pt-25))'
+ dcga='dcg_va*(1+tc1ab*(pt-25)+tc2ab*(pt-25)*(pt-25))'
+ dvg0a='dvg0_va*(1+tc1ac*(pt-25)+tc2ac*(pt-25)*(pt-25))'
+ vgnorma='vgnorm_va*(1+tc1ad*(pt-25)+tc2ad*(pt-25)*(pt-25))'
+ cgminp='cgmin_vp*(1+tc1pa*(pt-25)+tc2pa*(pt-25)*(pt-25))'
+ dcgp='dcg_vp*(1+tc1pb*(pt-25)+tc2pb*(pt-25)*(pt-25))'
+ dvg0p='dvg0_vp*(1+tc1pc*(pt-25)+tc2pc*(pt-25)*(pt-25))'
+ vgnormp='vgnorm_vp*(1+tc1pd*(pt-25)+tc2pd*(pt-25)*(pt-25))'
c in out '(area*(cgmina+dcga*(1+tanh((v(in)-dvg0a)/vgnorma)))+peri*(cgminp+dcgp*(1+tanh((v(in)-dvg0p)/vgnormp))))*nf'
.ends lvar_cap
*
.ENDL LVAR_CAP

I want to conversion functions above, is possible?

send your opinion, please... i'll wait. good bye

Best Regards

Title: Re: scalable varactor model
Post by Ken Kundert on Jul 13^th, 2005, 10:40am

You can certainly translate this model to Verilog-A, but you should know that the model is not charge conserving and so should not be used in charge storage circuits of if Q is important. For more information see http://www.designers-guide.org/Modeling/varactors.pdf.

-Ken

Title: Re: scalible varactor model
Post by Andrew Beckett on Jul 13^th, 2005, 2:12pm

Also, the above subckt can be simulated directly in spectre with no syntax changes from IC5141 onwards. In IC5141, you need to do:

Code:

spectre +csfe netlist.hsp

whereas in the latest simulator release, MMSIM60, the new front end (enabled by +csfe in IC5141) is on by default. The new front end gives improved performance (memory and speed) in the netlist parsing of spectre syntax, and also supports natively SPICE syntax files.

This is of course with Ken's proviso taken as read.

Regards,

Andrew.