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Design Languages >> Verilog-AMS >> Write to file
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Message started by noreng on Jul 18^th, 2005, 11:42pm

Title: Write to file
Post by noreng on Jul 18^th, 2005, 11:42pm

How do I write simulation results to a file?

Title: Re: Write to file
Post by Eugene on Jul 19^th, 2005, 8:52am

Since you posted this question under VerilogAMS I assume you want to know how to write data to a file within a VerilogAMS module. I do this all the time with VerilgoA, which should work in AMS. Suppose you want to sample and record V(out) and V(in) every deltaT seconds. Try

parameter real deltaT=1u;//for example.
real integer fptr;
...
analog begin
@(initial_step) begin
fprt = $fopen("file path");
end
...
@(timer(1p,deltaT) begin
$fstrobe(fptr,"%g %g",V(in),V(out));
end
...
@(final_step) fclose(fptr);
end

Title: Re: Write to file
Post by noreng on Jul 20^th, 2005, 1:41am

I've followed your advice, but it doesn't work.

The following code

@(timer(1p,deltaT)) begin
$fstrobe(fptr,"%g %g",reff1, reff2);
end

leads to the following error message:

'src/cswb_4_file.vla', line 108: Error : Illegal identifier specified. Identifiers starting with '$' must identify system tasks or functions.
'src/cswb_4_file.vla', line 108: Error : 'fstrobe' must be a variable.
'src/cswb_4_file.vla', line 108: Error : Syntax error
'src/cswb_4_file.vla', line 108: Error : Syntax error near '('.

Thanks in advance.

Title: Re: Write to file
Post by Andrew Beckett on Jul 20^th, 2005, 3:52am

I think from a previous posting, you are using Eldo. The $fstrobe certainly works in spectre.

I took a look at the LRM http://www.designers-guide.org/VerilogAMS/VlogAMS-2.2-pub.pdf (well, that's the abridged version), but that doesn't mention $fstrobe. Rather bizarrely it discusses $fopen/$fclose, but it's not obvious what you'd do with the results of these functions...

Haven't got time to look further right now.

Andrew.

Title: Re: Write to file
Post by Geoffrey_Coram on Jul 20^th, 2005, 4:30am

The $f-functions are defined in the IEEE 1364 Verilog Language Reference Manual, from which the Verilog-AMS LRM is derived.

Apparently, the AMS $fopen/$fclose system tasks are slightly different, and hence are defined for AMS in the AMS LRM, but the tasks to do anything with the opened file are identical to the 1364 definitions, and thus are omitted. I think that makes it hard to use the AMS LRM, but fixing that wasn't in the project scope when I updated the LRM to 2.2.

1364-1995 Verilog has $fstrobe $fdisplay $fwrite as well as a few special versions of these for binary data. I'm surprised that any simulator would not have these, since they've been in the language for years. (The 1995 version had only limited provision for *reading* from a file.)

BTW, the full 2.2 AMS LRM is available from
http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.2/AMS-LRM-2-2.pdf

-Geoffrey

Title: Re: Write to file
Post by noreng on Jul 20^th, 2005, 4:32am

If there are any Eldo users who are reading this.

If the $fstrobe is replaced by $fwrite, it is possible to write to file.

The rest of the code can be used as is.

Title: Re: Write to file
Post by Andrew Beckett on Jul 20^th, 2005, 10:42pm

Thanks Geoffrey - I was sure this was part of the language (should have remembered that it's standard Verilog), but didn't have time yesterday to look it up properly.

Andrew.

Title: Re: Write to file
Post by Jess Chen on Jul 21^st, 2005, 8:39am

Does Eldo support VerilogAMS or just VerilogA?

-Jess

Title: Re: Write to file
Post by noreng on Jul 21^st, 2005, 11:32pm

Eldo supports both.

If you are including a Verilog-AMS file in an eldo testbench, you have to use
vasim testbench
instead of
eldo testbench

Title: Re: Write to file
Post by Jess Chen on Jul 22^nd, 2005, 12:07am

Interesting. Thanks for the information.

-Jess

Title: Re: Write to file
Post by jbdavid on Oct 17^th, 2005, 1:25am

Just to clarify based on MY observations with one vendors tool - the way you open, close and write to files is a little different if you do it in the analog or digital domains.. - Pay close attention to IEEE-1364 when working in an "always" or "initial" block, and
closer attention to the Verilog-AMS LRM when working in an analog block.. or when writing Verilog-A models .. At least for now.
Jonathan

Geoffrey_Coram wrote on Jul 20^th, 2005, 4:30am: