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Design Languages >> Verilog-AMS >> Question about MUX
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Message started by MokoKoya on Aug 8^th, 2005, 7:51am

Title: Question about MUX
Post by MokoKoya on Aug 8^th, 2005, 7:51am

hello

I'm trying to model a mixed-signal mux4x1 which is digitally controlled. I really don't understand what I'm doing wrong in this model. I have a problem when it comes to the simulation. The error from the simulation log is as follows:

the following branches form a loop of rigid branches (shorts) when added to the circuit:

mux4x1_ana_tb V2:p (from mux4x1_ana_tb.x2 to ground)
mux4x1_ana_tb V4:p (from mux4x1_ana_tb.x0 to ground)
mux4x1_ana_tb V1:p (from mux4x1_ana_tb.x1 to ground)

I have 4 voltage sources as my inputs (nets x0 to x3), and a load resistance on the output. I am also using an example of a switch from the Verilog AMS designers guide page 115, 3.2.1 . Here is the code that I am using:

module MUX_ANALOG_2 ( OUT, IN0, IN1, IN2, IN3, SEL);

//===================//
// Ports Declaration //
//===================//

inout IN0, IN1, IN2, IN3;
input [1:0] SEL;
inout OUT;
electrical OUT, IN0, IN1, IN2, IN3;

//================//
// Analog Process //
//================//

analog begin

if (SEL==2'b00) begin
V(OUT, IN0) <+ 0.0;
I(OUT, IN1) <+ 0.0;
I(OUT, IN2) <+ 0.0;
I(OUT, IN3) <+ 0.0;
end else if (SEL==2'b01) begin
I(OUT, IN0) <+ 0.0;
V(OUT, IN1) <+ 0.0;
I(OUT, IN2) <+ 0.0;
I(OUT, IN3) <+ 0.0;
end else if (SEL==2'b10) begin
I(OUT, IN0) <+ 0.0;
I(OUT, IN1) <+ 0.0;
V(OUT, IN2) <+ 0.0;
I(OUT, IN3) <+ 0.0;
end else if (SEL==2'b11) begin
I(OUT, IN0) <+ 0.0;
I(OUT, IN1) <+ 0.0;
I(OUT, IN2) <+ 0.0;
V(OUT, IN3) <+ 0.0;
end else begin
I(OUT, IN0) <+ 0.0;
I(OUT, IN1) <+ 0.0;
I(OUT, IN2) <+ 0.0;
I(OUT, IN3) <+ 0.0;
end

end

endmodule

What is the problem? ???

Title: Re: Question about MUX
Post by Eugene on Aug 8^th, 2005, 11:13am

I am not certain but I wonder if this is some sort of simulator or netlister parsing problem. A parser, as I am using the term, looks for things that will cause simulations problems and flags them before running the simulation. The parser may not be smart enough to know that only one input is selected at a time. i.e. If you ignore the "if" statements and merely look for shorts based on the expressions, you would see all inputs selected at the same time. Since the inputs are driven by voltage sources, the parser thinks your mux is shorting voltage sources together at the common output. Truly shorted voltage sources would generate infinite current and crash the simulation. You might try giving your drive sources a small series input resistance, like 10 micro Ohms, just to sneak past the parser. The simulator should be smart enough to see that you are not actually shorting the inputs.

I would also consider using a "case" statement instead of "if" statements. The case statement was designed for this application. Perhaps the parser understands case statements. Although I suspect that if the parser chokes on if statements, it chokes on case statements too.

-Jess

Title: Re: Question about MUX
Post by Andrew Beckett on Aug 8^th, 2005, 9:34pm

The check for a loop of rigid branches gets a bit confused by complex switch branch structures. Now, if you're sure that there really isn't a loop (it looks like it), you can add an attribute before the analog block indicating that it should not do the check:

Code:

(* no_rigid_switch_branch *) analog begin
...
end

We decided it was too difficult to make the check able to spot every possible loop, and so this was the solution that was created. You need to be using spectre from MMSIM60 for this attribute to be supported. Unfortunately the attribute is not yet supported in AMS Designer.

My Sourcelink solution 11021530 covers this in a bit more detail.

Regards,

Andrew.

Title: Re: Question about MUX
Post by MokoKoya on Aug 9^th, 2005, 2:20am

Thank you Eugene for the solution with the resistances. It worked very well. And thank you Andrew for the solution with the (* no_rigid_switch_branch *) code.

Andrew Burton

Title: Re: Question about MUX
Post by Geoffrey_Coram on Aug 18^th, 2005, 10:29am

Another trick I've sometimes used when dealing with switch branches is to declare both the V and I branches:

branch (a,int) br_rs;
branch (a,int) rs_short;

analog begin
if (rs > 0)
I(br_rs) <+ V(br_rs) / rs;
else
V(rs_short) <+ 0;

end