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Design Languages >> Verilog-AMS >> VCO model from the Verilog-AMS section
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Message started by svensl on Aug 11^th, 2005, 7:12am

Title: VCO model from the Verilog-AMS section
Post by svensl on Aug 11^th, 2005, 7:12am

I was wondering whether there is a way of modelling the VCO from the AMS section so that it accepts negative voltages and has the lowest output frequency when the input is at its most negative value. I initially changed the switching points for the phase to also take negative values into consideration; however, then I will end up with the same output frequency for two identical input values, one being positive and one being negative. Can anyone please suggest a way of having a VCO accepting negative input values?

Thanks.

Title: Re: VCO model from the Verilog-AMS section
Post by Andrew Beckett on Aug 11^th, 2005, 9:29pm

Can you post the model you have? It's hard to see why this should be a problem without some idea as to what your model looks like.

Most VCO models tend to work by converting the input voltage to a frequency (gain*V(in)+fc) and then integrating that (using idtmod), and then using this as the phase for sin() or cos(). If modelled like this, negative input voltages wouldn't be a problem - provided that the overall frequency remains positive.

In other words:

Code:

inst_freq = gain*V(vin)+fc;
phase = idtmod(inst_freq,0,1);
V(vout) <+ amp*sin(2*`PI*phase);

Regards,

Andrew.