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Modeling >> Semiconductor Devices >> Excess thermal noise for short-channel CMOS
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Message started by vivkr on Aug 11^th, 2005, 11:39pm

Title: Excess thermal noise for short-channel CMOS
Post by vivkr on Aug 11^th, 2005, 11:39pm

Hi,

I would be grateful if someone could suggest a good way of accounting for excess thermal noise in CMOS transistors when the channel length is small. I know that there is an increase in measured noise which is largely dependent on the process and strangely enough, this is never included in the models despite this. Various theories abound on the net where some people suggest that the noise power is 3-4 times higher for L < 1um. Others say that noise voltage is higher by the same amount etc. A recent JSSC paper says that the excess noise is very small in opposition to all these theories (JSSC, Mar. 2005, Han et. al, "Complete High-Frequency Thermal Noise Modelling ....)

I am working with a 0.8um process and trying to design a very high-performance, low-noise opamp. Hence I am faced with the dilemma of using min. length input transistors or not.

Any hints?

Thanks
Vivek

Title: Re: Excess thermal noise for short-channel CMOS
Post by Paul on Aug 13^th, 2005, 8:31am

Vivek,

all depends on the important specifications of your design. If gain is more important than raw speed, you will anyway want to avoid using minimum channel length. Excess thermal channel noise is among others related to velocity saturation, which mainly happens in deep sub-micron technologies. I am not sure this is so critical in the technology you are using.

If your devices happen to work in this regime, you may experience excess thermal noise, but also reduced transconductance (thus less gain and gain-bandwidth). For this reason, except when you are working at the speed edge of the technology, it is always preferrable to avoid minimum length devices in the amplifiers.

Paul