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Message started by easyads on Aug 13th, 2005, 3:27pm

Title: problem about voltage reference buffer for ADC
Post by easyads on Aug 13th, 2005, 3:27pm

I am working on a high speed pipeline ADC. I have designed a bandgap circuit. The voltage from bandgap must be buffered to drive the reference pin of ADC such as Vrefp, Vrefn and Vcom. How can we ensure that the voltage refence buffer can settle to a desired resolution in half of clock period?  Does the buffer need large external capacitor? Could you please give me some idea reference, web resorce voltage reference buffer design in high speed design?

Title: Re: problem about voltage reference buffer for ADC
Post by vivkr on Aug 15th, 2005, 2:30am

Hi,

Yes, I think using an external capacitor might be the easiest solution. If you were not designing a pipelined ADC (and hence had a smaller capacitive load), then it might have been possible to design a high-speed voltage follower to achieve the same end. But, this will require extra power and the settling of the buffer must be quite good here.

One important point is that you design your DAC for each stage in such a manner that it presents a signal-independent load to the reference voltage. Otherwise, you will see increased distortion as the DAC charges or discharges the VREF in a signal-dependent manner, and incomplete settling on the VREF translates to harmonic distortion. DAC structures of this type are widely used, and one example may be found in the book by Norsworthy, Schreier and Temes on Delta-Sigma Converters. I believe it is in the chapter authored by B. Brandt which deals with analog circuit design. Use of such a DAC will reduce the settling accuracy requirements on your reference voltage as a constant settling error merely translates to an overall gain error which is more  benign.

You should be careful to use a large enough cap of the appropriate type and design your board well.

Good Luck!
Vivek

Title: Re: problem about voltage reference buffer for ADC
Post by Anurag Pulincherry on Aug 24th, 2005, 6:31pm

Hi,

you can feed the bandgap voltage in to a very slow buffer. The buffer only serves to isolate the original referance voltage generator from the switching noise. To the output of the buffer is taken off-chip,  and bypassed say by a 0.01uf in parallel with 0.1uf, they supply all the required charge.

Typically  you might have to add a series damping resistor to the capacitor to damp out any oscillations, due to the inductance inherent in the bond wire, board trace etc. Inaddition you also have to model, the inductance of the bus inside the chip that routes the reference. It is advisable to use a flipchip package with multiple bondpads allocated for reference  to minimize parasitic inductance.

There are not many references available, try

The scheme here is slightly different, does not use a buffer but just a resistor ladder with external bypass, the principle is the same.

A Highly Integrated Analog Baseband Transceiver
Featuring a 12-bit 180MSPS Pipelined A/D Converter for
Multi-Channel Wireless LAN, K. Gulati, C. Munoz, S.
Cho, G. Manganaro, M. Lugin, M. Peng, A. Pulincherry,
J. Li, A. Bugeja, A. Chandrakasan and D. Shoemaker,
Engim, Inc., Acton, MA

There is also a paper from Analog devices by Larry singer, don't quite remember which one.

Title: Re: problem about voltage reference buffer for ADC
Post by easyads on Aug 24th, 2005, 9:06pm

Thanks for your reply.
But i can not find the paper through google.
Would you please be so kind to email me the paper  "A Highly Integrated Analog Baseband Transceiver
Featuring a 12-bit 180MSPS Pipelined A/D Converter for
Multi-Channel Wireless LAN, K. Gulati, C. Munoz, S.
Cho, G. Manganaro, M. Lugin, M. Peng, A. Pulincherry,
J. Li, A. Bugeja, A. Chandrakasan and D. Shoemaker,
Engim, Inc., Acton, MA "?

And my email is easyads@163.com.


Title: Re: problem about voltage reference buffer for ADC
Post by ywguo on Aug 24th, 2005, 10:24pm

easyads,

Please refer to
http://www.designers-guide.org/Forum/?board=ms_design;action=display;num=1093223640


Yawei

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