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Other CAD Tools >> Physical Verification, Extraction and Analysis >> LVS transmission lines with Calibre and Cadence
https://designers-guide.org/forum/YaBB.pl?num=1124194344

Message started by microwave_jim on Aug 16^th, 2005, 5:12am

Title: LVS transmission lines with Calibre and Cadence
Post by microwave_jim on Aug 16^th, 2005, 5:12am

Hi,

I have a lumped model consisting of ideal L, R & C elements to represent a microstrip transmission line in my Cadence schematic and I am trying to make this LVS (using Calibre LVS) with a strip of top-layer metal (over a ground plane) in my Cadence Virtuoso layout.

I understand that that there is some sort of cookie-cutter method whereby I can have the schematic and layout match up by name if there are the same number of terminals even though the internals don't match up.

Any help with my problem is greatly appreciated.

Cheers
Jim

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by Paul on Aug 18^th, 2005, 2:23am

Jim,

you can ask Calibre to ignore a given type of resistors, capacitors etc in either the schematic or layout netlist (or both) by considering them as opens or shorts. Or you build a black box for both your layout and schematic, but that's the solution you already mention in your post.

I cannot see a different solution (like marking layers) due to the distributed nature of the microstrip line.

Don't hesitate to ask if you need more information about this.

Paul

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by microwave_jim on Aug 18^th, 2005, 5:22am

Hi Paul,

Thanks for the reply. The problem is that I know that you can do some sort of black box thing, but I don't actually know how to do this with Calibre. Could you point me in the direction of a soloution or some documentation.

Cheers

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by Paul on Aug 19^th, 2005, 4:50am

Jim,

do you have access to Mentor Graphics SupportNet? If so, there are appnotes explaining the detailed approach. Otherwise, have a look at the SVRF (Standard Verification Rule Format) Manual, Reference Dictionary, "LVS Box" statement. You have to add such a statement using the following syntax

LVS Box SOURCE LAYOUT cell_name

where cell_name is obviously the name of your black box. The tool will assume that the inside of this box has already been checked and just consider the terminals (which of course should match between schematics and layout).

Of course you first have to create this cell containing a) the microstrip model on the schematics side and b) the metal wire on the layout side.

Hope this helps

Paul

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by microwave_jim on Aug 21^st, 2005, 2:58pm

Hi Paul,

That's it! I really appreciate your help.

Cheers
James

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by microwave_jim on Aug 22^nd, 2005, 5:21am

Hi Paul,

So I now get that you have to add the LVS BOX statement to the rules file, however, beceause my transmission lines are just currently represented by just a signle top-layer metal trace (microstrip lines), the input pin and output pin are on the same layer and therefore Calibre LVS shorts the two pins.

Is there anyway to prevent Calibre LVS from shorting these two pins?

Cheers
Jim

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by Paul on Aug 22^nd, 2005, 8:07am

Right Jim,

I forgot that "detail". Maybe there is a solution through LVS statements I do not realize right now, but I believe you need to add a marker layer to separate both pins of your microstrip line. Add a marker layer to your layout layers and put it as a rectangle overlapping the metal wire between both pins.

Then you need to add a component rule to your LVS rules, you can use the one typically used for resistors (they are drawn this way). Extract a resistor of any value, as it appears in the black box, it will not be compared. Check the DEVICE statement in the SVRF manual, it should be something like:

DEVICE R (R_fake) RDUM METx METx (POS NEG)

where Rfake is a fake model name, RDUM is the layer name you obtained from layer derivation (RDUM = METx AND MARK_LAY)

Nothing needs to be changed in the schematic view, as the box is already OK.

Paul

Title: Re: LVS transmission lines with Calibre and Cadenc
Post by microwave_jim on Aug 24^th, 2005, 5:54am

Hey Paul,

I think that I have finally done it (with your help of course). My transmission lines finally pass LVS. Again, thank you for all your help, I really appreciate it.

Cheers
Jim