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Design >> High-Speed I/O Design >> question on lvds
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Message started by navin_kumar on Aug 24^th, 2005, 1:54am

Title: question on lvds
Post by navin_kumar on Aug 24^th, 2005, 1:54am

Hi all
in the LVDS transmitter
we need multi phases front the reference clock
then we can generate the required clock phases from the input clock it self
then what is the need for the pll
and which is used for frequency multiplication

Title: Re: question on lvds
Post by Bharat Srivastava on Aug 31^st, 2005, 5:42am

I am not very clear from the question, but i can explain the reason for frequency multiplication.

As LVDS is serial interface, it converts data from parallel to serial. therefore clock needs to be multiplied by 7x (x is the clock freq at the core), if 8 bit data are coming fromt the core at the tick of the clock.

let me know whether I answered ur question.

thanks
-Bharat

Title: Re: question on lvds
Post by ywguo on Aug 31^st, 2005, 5:55pm

Hi, Bharat,

Why does the clock need to be multiplied by 7x for 8 bit data from the core? Is it a typo error?

It should be 8x for 8bit data, or 8 phase for 8 bit data.

Best regards,
Yawei

Title: Re: question on lvds
Post by bsrivastava on Sep 1^st, 2005, 3:51am

Yawei,
Sorry, It is a typo, I am serializing 7 bits coming from the core not 8 bits. I am getting the serialized data at my inout of predriver
The very first edge of clock freq x and 7x is common.

Title: Re: question on lvds
Post by navin_kumar on Sep 8^th, 2005, 12:20am

hi, bharat
ur correct
for serializing 7 to single it requires that many phases to make the datarate that much faster than the input
if we r going to serialize a 28 bits or 30 multiplier of 30 or 28 and it will increse the vco output frequency and automatically power consumption
--main aim is tminimization of power consumption and transfer the datarate at that high speeds
please give me any good link on lvds exept national.com