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Design >> Mixed-Signal Design >> PSRR of Voltage regulators
https://designers-guide.org/forum/YaBB.pl?num=1124960019

Message started by ramakrishna on Aug 25^th, 2005, 1:53am

Title: PSRR of Voltage regulators
Post by ramakrishna on Aug 25^th, 2005, 1:53am

Hello all,
I have designed a voltage regulator for a low speed piplened ADC. I have used folded cascode first stage and common source second stage with a resistive ladder load to produce the references for the MDACs.
I have used cascode compensation take the capacitor from folding point of the first stage to the output of the second stage.
I have two questions:

1. I am still having the problem of PSRR at high frequenies as it getting close to 0dB. Is there any other technique to improve the PSRR.

2. Will putting resistor before capacitor along with the cascode compensation help me.

I will be lot of help to me if someone can give me good references in understanding the psrr issues.

Thanks,
RK

Title: Re: PSRR of Voltage regulators
Post by Paul on Aug 25^th, 2005, 12:35pm

Hello,

for frequencies above the regulator bandwidth, the PSRR is defined by the capacitive coupling ratio between aggressor (Vdd to Out) and grounding (Out to GND) capacitance. Reducing the former or increasing the latter will improve the PSRR at high frequencies.

I hope this answers your question.

Paul

Title: Re: PSRR of Voltage regulators
Post by ramakrishna on Aug 26^th, 2005, 7:55pm

Hello Paul,
Thanks for the quick response. Yes it improves the psrr at higher frequencies.

Any references

1. That derive psrr at high frequencies for opamps.

2. that explain the psrr improvement techniques for two stage opamps.

Thanks,
RK