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Design >> Mixed-Signal Design >> capacitor matching >=10b
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Message started by ramakrishna on Aug 30^th, 2005, 8:51am

Title: capacitor matching >=10b
Post by ramakrishna on Aug 30^th, 2005, 8:51am

Hello all,
I am doing layout to obtain three equal capacitors(1:1:1). I am using MIM(metal1 to metal4) capacitors and doing a common centroid layout to obtain a matching of about 10b. I am using Metal4 and Metal5 for routing. Metal1 through Metal4 are exactly overlapped to form a square-shaped unit capacitor. I am connecting Metal1 and metal3 at bottom left, metal2 to metal4 at top right through vias. I am taking interconnect lines from the same points.

I have following questions on the layout.

1. Long interconnect routing metals side-by-side causing a signicant amount of mismatch. How do we reduce it or match it.
2. Unit capacitor placed next to one-another are summing upto significant capacitor mismatch. Is increasing the distance between the capacitor the only solution to reduce those parasitic capacitors?
3. I have seen couple of documents online, modifying the edges of the squares to compensate for etching mismatches in corners for poly-poly capacitors. Will it be applicable for MIM capacitors also? If yes, which metals have to be modified.

Please let me know of any references/links that can help me with capacitor matching >=10b.

Hoping to get a response.

Thanks,
Ramakrishna

Title: Re: capacitor matching >=10b
Post by Paul on Aug 30^th, 2005, 1:54pm

Ramakrishna,

First I wanted to mention that in most commercial mixed-mode processes, MiM stands for a particular capacitor using only two levels of metal with a thin oxyde layer in between. This eases some issues discussed below.

Some answers to your questions:
1. Try to keep them as short as possible by optimizing the capacitor arrangement.
2. The fact that standard MiM and PP caps use only two layers reduces this effect. Spacing will indeed help, but is expensive.
3. Identical environment for all capacitors should be sufficient to keep etching mismatch low.

I however doubt you will be able to achieve 10b matching. Could you describe your application and design to explain why you have such stringent matching constraints. Wouldn't a dynamic element matching scheme solve your problem?

Paul

Title: Re: capacitor matching >=10b
Post by ramakrishna on Aug 31^st, 2005, 6:14am

Hello Paul,
Thanks for the quick reply. I am designing a 10b, 1Msamples/sec, two stage cyclic RSD ADC. The input to the ADC is a single-ended with a voltage swing of 0 to 3V. The first stage not only samples the input but also scales it down to 1.5V swing. To achieve this I am using an extra capacitor alongwith the two sampling capacitor generally available in MDAC. The second stage, which is an single-ended 1.5bits/stage MDAC, then produces the residue which is fed back to input stages which now acts as another MDAC. The process repeats till 10bits are obtained. Thus, a capacitor matching upto 10b in both stages is required.

Some papers say that 10b matching precision is feasible with proper layout techniques, but I am not sure.
Any suggestions regarding the architecture or layout issues will be great help to me.

Thanks,
Ramakrishna

Title: Re: capacitor matching >=10b
Post by Anurag Pulincherry on Aug 31^st, 2005, 10:15pm

Hi,

I am not sure the technology that you are using. I have seen better than 11.4 bits matching in 0.25 um cmos process, with conventional layout techniques. One way see this is to run (let us say u have a high speed 200 msps ADC) adc at say 75 msps. Now the error is dominated by cap mismatch. I have seen about 11.4 bit enob or sndr for a 13-bit resoultion adc

restict the signal flow in one direction in the array. example: input switches connected to the bottom plate, all on the lower part ofthe array. The top plate routing, all on the upper side goes to the opamp virtual gnd. That should help.

do not cross routing on top and bottom plate of the same unit cap . This will directly add parasitic to the explcit cap.

I am not sure why u are using metal1 for mim caps . usually they use higher level metals with special dielectic in between. Also make the bottom plate larger to reduce fringing fields.

Back annotate the routing both r and c into the schematic.

try

http://www-mtl.mit.edu/~daihyun/papers/designmethodology/centroidcap.pdf

for more insights.

Title: Re: capacitor matching >=10b
Post by ramakrishna on Sep 1^st, 2005, 7:45pm

Hello Anurag,
Thanks for the response. You are right, I have seen papers without calibration or trimming achieving good ENOB. But at the same time there are lot of 10b ADC papers that use calibration techniques. Berkeley pipeline ADC papers mention that 8-9b of matching is the limit of the layout techniques. Most of their papers use trimming techniques.

This leads to few questions,

1. Some of the few ADC papers which dont use calibration and getting good ENOB, are they using some refined or accurate processes or is it possible with Standard CMOS technology using some very systematic layout schemes.
2. For a standard CMOS process what is the best ENOB that can be achieved without Calibration.

I am currently designing an ADC for 90nm, so it is a costly deal for the company. Any suggestions will be of great help.

Thanks,
Ramakrishna

Title: Re: capacitor matching >=10b
Post by Paul on Sep 2^nd, 2005, 12:24am

Hello,

I believe true MiM capacitors are more linear and well-controlled in terms of processing steps than the plain metal capacitors you are trying to use. Probably MiM is not (yet) available in your 90nm process, so I understand your choice. Still, considering the mask cost (in case of respin) in such a process, I would chose a robust solution (calibration) if the functionality of the system totally depended on the capacitor matching.

Paul