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Design Languages >> Verilog-AMS >> how to overwrite a file in Veriloga?
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Message started by tumeda on Sep 1^st, 2005, 10:03am

Title: how to overwrite a file in Veriloga?
Post by tumeda on Sep 1^st, 2005, 10:03am

Who can tell me how to overwrite a file in Veriloga?

I use these commands " $fopen(fp) & $fstrobe(fp, ...) & $fclose(fp)" to write the output periods of a PLL into a file. If I do a simulation again, the output results are just added into the previous results. How can I firstly delete the old simulation results, then wirte new simualtion results into the file. :'(

Thanks a lot!!!

Title: Re: how to overwrite a file in Veriloga?
Post by Geoffrey_Coram on Sep 1^st, 2005, 11:23am

The $fopen system function defined in 1364-1995 (from which Verilog-AMS is defined) did not have an argument for opening in read/write/append text/binary. Curiously, the LRM does not say whether $fopen was supposed to append or truncate. (Probably some simulators do one thing, and others do another.)

The extra argument was added in 1364-2001, so you may find that your simulator does, in fact, support the argument. (Vendors had to implement it for digital Verilog, so why not allow the functionality in V-AMS?)

$fopen("filename", "w")

Title: Re: how to overwrite a file in Veriloga?
Post by tumeda on Sep 2^nd, 2005, 1:58am

Geoffrey_Coram, thank very much!

you are right. The following is found in CDSDOC file.

fopen_function ::= multi_channel_descriptor = $fopen ( "file_name" [ "io_mode"] ) ;
.....
io_mode is one of three possible values: w, a, or r. The w or write mode deletes the contents of any existing files before writing to them. The a or append mode appends the next output to the existing contents of the specified file. In both cases, if the specified file does not exist, $fopen creates that file. The r mode opens a file for reading. An error is reported if the file does not exist.

I added the option in the code, but the simulation results is always appended to the old results? What's a problem? ???

Title: Re: how to overwrite a file in Veriloga?
Post by Geoffrey_Coram on Sep 2^nd, 2005, 4:37am

If the simulator behavior doesn't match the documentation, then you should file a bug report with the vendor.

Do the results get appended even if you completely restart? Ie, Spectre allows you to put multiple analyses in a single netlist and maybe it appends everything from the same netlist, but if you run the whole netlist again, do the results still get appended? Do you have any @(initial_step) code around your $fopen? There was some ambiguity in the LRM as to what initial_step meant for DC, and some simulators re-use a single DC op-point to compute multiple AC analyses, so maybe initial_step isn't happening.

Title: Re: how to overwrite a file in Veriloga?
Post by tumeda on Sep 2^nd, 2005, 5:09am

Thanks a lot for Geoffrey_Coram' help!

I made a mistake in my veriloga Model. :P

I used "if $realtime==25e-6, $fclose(fp)" to close the file, but actually the file is not closed. Hence the simulation results are always appended into the file.
Now I corret the syntax to "if $realtime>=25e-6, $fclose(fp)". It works now in order. :D
I have great fun to discuss problems at hier!

Title: Re: how to overwrite a file in Veriloga?
Post by Geoffrey_Coram on Sep 2^nd, 2005, 7:56am

I'm guessing that you don' t need the mode argument "w" -- that this is the default, and that your original problem was just that you weren't properly closing the file.

Am I right?

Title: Re: how to overwrite a file in Veriloga?
Post by tumeda on Sep 2^nd, 2005, 10:05am

yes, u are right!