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Design >> Mixed-Signal Design >> question :12-bit pipeline ADC
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Message started by juzi on Sep 6^th, 2005, 8:31am

Title: question :12-bit pipeline ADC
Post by juzi on Sep 6^th, 2005, 8:31am

hi,all

I want to design a 12-bit 100-MS/s pipelined ADC, I have not experence, Is there some special consideratin with so high resolution?
Is it too difficult for a beginner?
Is it better for me just design a 10-bit 100MS/s pipeline ADC ?

thanks

Title: Re: question :12-bit pipeline ADC
Post by Paul on Sep 6^th, 2005, 12:18pm

Hi Juzi,

I don't know what exactly you qualify as "a beginner" (undergrad student, B.S., M.S., junior designer,...?) and what is the goal of your design (student project, academic research, industrial project?), and I don't either know the technology you are going to use, but you should be aware that 10b 100MS/s is already quite close to the current state of the art. There are probably too many things to consider to pretend this to be an exhaustive list:

- thermal noise
- OTA design (settling time, slew rate, DC gain, ...)
- all the switched-cap things (charge injection, clock phase generation, clock feed-through, parasitic capacitances)
- clock jitter in S&H
- error correction for high resolution
...

If you have experience in OTA design and switched-capacitor design, you should be able to address these issues, but if you are a beginner in all these fields and if the work must comply with the specifications you set now, I would recommend to target a somewhat lower data rate and not more than 8-10b. In the open literature (e.g. IEEE collection), you will notice that for higher resolution people use error correction schemes, which definitely result in a more complex design.

Paul

Title: Re: question :12-bit pipeline ADC
Post by juzi on Sep 6^th, 2005, 7:43pm

Hi Paul,

It's very glad to see your replay. I'm a Postgraduate student majored in Microelectronics,Grade 2. the goal of my design is stident project. I wanna to use UMC.18 Process, CMOS, the minimum channel length is 0.34u for analog circuit.

Title: Re: question :12-bit pipeline ADC
Post by juzi on Sep 6^th, 2005, 7:58pm

thermal noise
- OTA design (settling time, slew rate, DC gain, ...)
- all the switched-cap things (charge injection, clock phase generation, clock feed-through, parasitic capacitances)
- clock jitter in S&H

I've read some papers about these issues. I've design a simple s/h circuit of a pipeline ADC(10-bit,33MS/s), however,it is just a student assignment. It is designed on circuit level with MOSFET, no layout,no tapeout. So I wanna to have a top-down ADC design with my classmates.

juzi

Title: Re: question :12-bit pipeline ADC
Post by Paul on Sep 7^th, 2005, 12:42pm

Juzi,

I guess you can either use the thick oxyde devices operating up to 3.3V (which you call analog) or the regular devices operating up to 1.8V. Why would you limit yourself to the former category? In that case, you could use a much cheaper 0.35um technology, except that the digital part would be somewhat larger. Possibly a design with 3.3V devices would achieve a somewhat better dynamic range, but it will have a hard time to achieve high sampling rates.

Regarding your experience, it may be interesting (if you can financially afford it) to have a tape-out with your S&H design and see if the chip complies with the specs. If you spend some time debugging it and learning about its limitations, you would probably be able to design a better ADC in the following.

Good luck

Paul