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Design >> Analog Design >> digital calibration algorithms for pipelined ADCs
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Message started by vivkr on Sep 10^th, 2005, 12:26am

Title: digital calibration algorithms for pipelined ADCs
Post by vivkr on Sep 10^th, 2005, 12:26am

Hi everyone,

I am looking for a good and easy-to-use digital calibration scheme for my ADC. There are several good papers in JSSC on this topic. However, I would like some suggestions from someone who has experience with these techniques.

I myself have never had to use calibration techniques so far and would like to know which ones have been found to be efficient (area and overhead). I cannot afford to put a very large ALU on chip and dont like the idea of altering my analog signal path too much by adding trim capacitors.

I currently have a dozen or so papers, all of which deal with various kinds of digital calibration, and it is hard for me to judge which one would be suitable.

Any feedback will be most welcome.

Thanks
Vivek