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Design >> Mixed-Signal Design >> simulation of ADC linearity
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Message started by Visjnoe on Sep 10^th, 2005, 9:54am

Title: simulation of ADC linearity
Post by Visjnoe on Sep 10^th, 2005, 9:54am

Hi,

I'm currently simulating the accuracy (ENOB) of an ADC. These simulations do not include noise (no transien noise analysis).

I perform an FFT on the simulation output and integrate the output spectrum (except for the fundamental tone) to determine SNDR and subsequently ENOB.

Typically, the spectrum looks like a noise floor plus some harmonics.

I'm now questioning the correctness of my approach: is it
valid to integrate the 'noise floor' to determine SNDR while the simulation does not contain noise? Am I not only integrating 'numerical' noise? Isn't it only THD that can be determined from such a simulation? So, just looking at the harmonics (caused by non-linearity of sub-blocks, MOS switches, capacitances etc.)

Can anyone provide some insight on this topic?

Thanks in advance!

Peter

Title: Re: simulation of ADC linearity
Post by Ken Kundert on Sep 10^th, 2005, 4:24pm

If you are simulating a "deterministic" ADC with no noise sources present, then any "energy" you find between the harmonics is simulator error. However, this is not true for noisy ADCs, such as delta-sigma converters, converters with random dither, etc.

-Ken

Title: Re: simulation of ADC linearity
Post by Visjnoe on Sep 11^th, 2005, 10:51am

Hi Ken,

thanks for your answer.

The ADC is in fact a pipelined converter. So if I understand you correctly, I should only take into account the harmonics and the 'noise' should be ignored because it is simulator error.

Can you provide some insight on what causes this noise floor/error? Is it the random dv on each voltage node when Newton-convergence is reached?

Thanks in advance!

Peter

Title: Re: simulation of ADC linearity
Post by Ken Kundert on Sep 11^th, 2005, 11:06pm

Correct.

There are several causes for error that appears as energy between the harmonics. They may include:
1. error due to inaccurate period
2. error due to residual transients
3. error due to aliasing
4. error due to interpolation
5. error due to various simulator noise mechanisms

The simulator noise mechanisms may include:
1. KCL tolerances
2. Various forms of bypass
3. variable time steps and breakpoints

These things are discussed in my book The Designer's Guide to SPICE and Spectre. Chapter 5 is full of this stuff.

-Ken

Title: Re: simulation of ADC linearity
Post by Anurag on Sep 16^th, 2005, 10:09pm

Hi,

Although thermal noise is absent, you should see quantization noise in the output spectrum, provided you give a fairly fast varying sine wave. It is not really noise, but very high order harmonics due to the finite no: of bits resolved. it will look like noise. so this may not be simulator error. In addition you'll also see harmoincs due to nonidealities like finie opamp gain, bw, distortion due to nonidealities in switches etc.

Anurag.

Title: Re: simulation of ADC linearity
Post by sheldon on Sep 28^th, 2005, 10:32pm

Visjnoe,

There are some aproaches for including noise effects
in the simulation:

1) Create a clock source with random jitter. This will
allow you to capture the sensitivity of the design to
aperature jitter or noisy clocks.

2) Also Spectre now supports large signal transient noise
analysis which would allow you to see the effect
transistor noise on the overall performance of the
design.

Also it may be easier to perform this analysis on the
just the Sample and Hold block rather than trying
to simulate the entire ADC. First it is easier[runs faster]
and for most designs the S/H limits the performance
anyway. This is important because you need to set the
simulator settings conservatively for large signal noise
analysis. Also, as Anurag pointed out the noise
floor of an ADC is limited by quantatization noise,
however, the noise floor of the S/H is limited by "real"
noise. So it is easier to analyze the circuits performance.

Finally, my experience is that this problem is a good
application for behavioral modeling. You really don't
need all the information that transistor level simulation
provide and you do need a lot of speed. Also the ability
to on and off noise sources is really useful for
understanding and eliminating noise issues.

Best Regards,

Art Schaldenbrand

Title: Re: simulation of ADC linearity
Post by jbdavid on Oct 2^nd, 2005, 5:07pm

And of course if you need example behavioral models for a pipelined converter.. you can borrow from the models described in the tutorial on the BMAS website - www.bmas-conf.org