The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> How to reduce PLL jitter? https://designers-guide.org/forum/YaBB.pl?num=1126784558 Message started by vijay on Sep 15th, 2005, 4:42am

Title: How to reduce PLL jitter? Post by vijay on Sep 15th, 2005, 4:42am Hi, I am trying to simulate a complimentry negative gm LC oscillator and use it in my PLL based synthesizer.I have a jitter measured through the process that Ken's paper describes. What would be the ways to reduce the jitter if the value which I come across after the simulationdoes not suit my specification?

The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved.