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Design Languages >> Verilog-AMS >> synthesizable non-integer delays
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Message started by Paul Geraedts on Sep 16^th, 2005, 4:11am

Title: synthesizable non-integer delays
Post by Paul Geraedts on Sep 16^th, 2005, 4:11am

Just wondering: is Verilog-D containing delays synthesizable? And more specifically: are non-integer delays synthesizable (for instance as part of an asynchronous controller)? What about the accuracy of such RC-delays? I know it's is almost analog design, but who knows it's possible!

Title: Re: synthesizable non-integer delays
Post by jbdavid on Oct 4^th, 2005, 5:55pm

Why would integer vs non-integer delays make a difference.. the delay is always referenced to a time-scale that determines the actual delay..
or are you thinking of UNIT delays?

since I deal in Behavioral models, rather than Synthesis I actually don't know much about the Synthesizable subset.. but it is covered in most courses and books on Verilog.. Perhaps even in the LRM..
Jonathan