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Other CAD Tools >> Unmet Needs in Analog CAD >> modelling of on-chip stress

Message started by vivkr on Sep 23rd, 2005, 4:22am

Title: modelling of on-chip stress
Post by vivkr on Sep 23rd, 2005, 4:22am


I think that one very useful feature could be a stress chart of a layout, given the kind of package used (plastic/ceramic). I am not certain if it would be extremely relevant, but atleast we should start to view our analog layouts the way they are - 3-dimensional.

Currently, the layout looks like a tangled net with lines of different colors running all over it. But, in reality, it is layer on top of layer, and with the existing computing capabilities, it should be very easy to provide a stress chart, allowing the user to also zoom in into an area and look at a 3-D view of the stress map or see if his gate poly is suffering significant stress or shear action.

This should help in deciding the effectiveness of a floorplan or dummy devices. After all, the on-chip stresses are not really random and can be predicted quite accurately, given the requisite information.

Of course, high levels of matching are specially desirable in precision bandgap circuits, while in the rest, one just tries to make a robust device. So this may just be a niche application.


Title: Re: modelling of on-chip stress
Post by Paul on Sep 24th, 2005, 6:24pm

Hi Vivek,

interesting idea. There was a paper on the effect of metal filling on MOS transistor matching by people from Philips some time ago (H.Tuinhout, M.Pelgrom et al., "Effects of Metal Coverage on MOSFET Matching", EDM '96). Sounds like it's a major issue and nobody cares about... I don't think only bandgap circuits are to be considered, but most analog designs (ADC, band-gap references, RF-ICs, ...).

One problem may be the dependency on foundry information related to etching and CMP, which is probably something they don't want to deliver as easily as device data. On the other hand I don't know (any manufacturing people in this forum?) whether this is really predictable and relatively constant from lot to lot.

One more thing is that the package may have a strong influence too on local mechanical stress ("Drift in Silicon Integrated Sensors and Circuits due to Thermo-Mechanical Stresses", Dragan Manic et al., Hartung-Gorre Verlag). As this depends on the packaging material, the packaging process and probably even the relative orientation of the liquid flow to the chip it may not be possible to consider in such a calculation.

Looking forward to your comments.


Title: Re: modelling of on-chip stress
Post by rf-design on Sep 27th, 2005, 1:54am

Before STI (Shallow Trench Isolation) there where only outdiffusions of wells and mechanical stress of the metal pattern impacting offset (beside the simple geometric view). With STI the stress is direct introduced into the substrate and depend on fill material. I acknowledge that there are growing number of analog important effects to model with an vanishing number of people understanding and puttting that into work.

Title: Re: modelling of on-chip stress
Post by vivkr on Sep 28th, 2005, 1:15am

Hi Paul,

You are right about there being several factors to account for, and naturally the reluctance of the foundries to provide some of the necessary information.

However, I think that a simpler yet useful solution could be found by a simple tool which does an approximate stress map. So, it could use incomplete information about the detailed foundry processing. I believe that most foundries do provide information about the layer thicknesses and mostly, the materials used are known, and so are their coefficients of elasticity etc. Therefore, it should be possible to get a stress map for the chip.

Packaging is surely one of the most important factors here as ceramic and plastic packages differ widely in the stress that they impart to the chip.

So, I would imagine that even with incomplete information, the designer can atleast see how uniform the stresses are in the critical  analog block when a certain amount of dummy devices are added, or the floorplan of the chip readjusted.

So, designers can place their critical blocks in places where there is less variation of stress and add the right amount of dummy devices.

I have in mind something similar to one of those substrate noise tools. They don't give precise information but an approximate noise map of the chip which allows designers to adjust their floorplans and place critical blocks away from noise generators, and also to see the effectiveness of guard rings. Essentially, these also offer relative noise contours but are not exact. A simple stress-mapping tool could be developed along similar lines using basic information which is readily available.

I think this might be quite useful already.


Title: Re: modelling of on-chip stress
Post by rf-design on Sep 28th, 2005, 10:29pm

Hi Vivek,

are you interessted in global stress introduced by the packaging or in local stress and imbalances by second order effects not modelled by the foundry?

For local mechanical stress, outdiffusion and overlayer shadow effects there could be models which extract from layout the right impacting effects. In practice all these effects are known to the analog IC designer and used as guideline for a matched layout construction. That reduce the total effort to put this into work. It favors therefore IDMs. The number of analog designs where some uV drift from package stress is impacting major system specs is very small. So it seems not  profitable to invest in tools and automated methods.

Title: Re: modelling of on-chip stress
Post by krishnap on Apr 24th, 2007, 2:56am

How the on-chip stress effects the functionality of the Bandgap and other sensitive analog circuits?
This is an interesting concept, as i have heard some of the Bandgaps are not working properly in the SOC's
because of stress.

Title: Re: modelling of on-chip stress
Post by Paul on Dec 3rd, 2007, 12:55pm


The piezo-junction effect on Vbe is described in the following reference.

I'm sure there are other papers around.


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