The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Cross-domain access in VerilogAMS https://designers-guide.org/forum/YaBB.pl?num=1127502230 Message started by chakrabartis on Sep 23rd, 2005, 12:03pm |
Title: Cross-domain access in VerilogAMS Post by chakrabartis on Sep 23rd, 2005, 12:03pm Hi, I have a couple of questions related to cross-domain access in VerilogAMS and I am hoping that the experts on this forum can answer those: 1) Let's say I have a design in which digital nets, reg, and variables are being read inside an analog block. 1.a) analog begin avar = dvar; //dvar is an integer/real variable owned by digital 1.b) analog begin if (dnet == 1'b1) //dnet is a digital wire 1.c) analog begin if (dreg == 1'b1) //dreg is a digital reg Should the simulator switch control to analog in all of the above cases if the value of the corresponding digital object changes? When is the value read on-demand, and when does it require context switching? 2) Similarly, let's say I have a design in which analog nets and variables are being read inside an always block. 2.a) always begin dvar = V(anet, gnd); //anet is an analog net 2.b) always begin dvar = avar; //avar is an analog integer/real variable Should the simulator switch control to digital in all of the above cases if the value of the corresponding analog object changes? When is the value read on-demand, and when does it require context switching? I will really appreciate if you could please reply to the above questions. Thanks and best regards, Sid. |
Title: Re: Cross-domain access in VerilogAMS Post by jbdavid on Oct 4th, 2005, 5:49pm Hm, OK let me start with 1.. first there are a couple ways to get the interaction in the analog engine.. 1. you can just ACCESS the value of logic signal.. this leaves the CONTROL of when the simulator puts a time step in completely up to the analog side.. - ie if you don't have anything else in the analog side forcing a time step while the signal is high, you may never observe it high in the analog side.. to force a timestep in the analog solver based on the digital signal you need to use an event this case might miss events on dreg Code:
this one uses the digital event to trigger the analog event Code:
Similarly if you just access the (analog) value in an always block on the digital side, the event controlling that block will determine when that value is updated.. so a block like Code:
may not see the event you want.. where Code:
will always force the digital engine event when the signal crosses.. simple way to remember it.. "event" style interaction will PUSH the value from the other solver.. "ACCESS" style interaction will PULL the value from the other solver.. Hope this helps.. jbd |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |