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Modeling >> Behavioral Models >> VHDL - Generate truth table ?
https://designers-guide.org/forum/YaBB.pl?num=1128214842

Message started by niakia on Oct 1^st, 2005, 6:00pm

Title: VHDL - Generate truth table ?
Post by niakia on Oct 1^st, 2005, 6:00pm

I am to create an entity "counter" that has three clocks(clk1, clk2, clk3) to generate a truth table consisting of all eight exhaustive binary values for the three signals. Assume clk1 is the least significant bit and clk3 is the most significant of a truth table.

-Can someone help me to determine what i should do next please ? I am very new to VHDL and in need of guidance ???.
________________________________________________________

ENTITY counter IS
END counter;

ARCHITECTURE behavioral OF counter IS
SIGNAL clk1, clk2, clk3: BIT;

Title: Re: VHDL - Generate truth table ?
Post by niakia on Oct 1^st, 2005, 10:52pm

nvm i got it ;D