The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Simulators >> Logic Simulators >> Disable timing check in NC-Verilog https://designers-guide.org/forum/YaBB.pl?num=1128908679 Message started by ywguo on Oct 9th, 2005, 6:44pm

Title: Disable timing check in NC-Verilog Post by ywguo on Oct 9th, 2005, 6:44pm Hello, I need to disable timing check for several instances on running post-layout simulation. The simulator is NC-Verilog. Does anybody know how to disable timing check (setup time and hold time) for only several instances in NC-Verilog? Thanks Yawei

Title: Re: Disable timing check in NC-Verilog Post by ekne on Nov 4th, 2005, 9:41pm Assuming you need to "remove" X propagation  :-/ NC-verilog +ncnonotifier still get the timing checks but no x generation due to timing checks. perhaps together with +ncno_tchk_msg to suppress the messages. The +ncnotimingchecks disables all as you probably know. //BEE

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