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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Extraction & Post-Layout Simulation Methodolog
https://designers-guide.org/forum/YaBB.pl?num=1129306482

Message started by vipul on Oct 14^th, 2005, 9:14am

Title: Extraction & Post-Layout Simulation Methodolog
Post by vipul on Oct 14^th, 2005, 9:14am

Hi

I extracted just a MOSFET using Assura, and it showed me parasitics on the terminals of the MOS. The IBM manual says that the MOSFET parasitics are included in the model and an extraction program should not calculate parasitics within the MOSFET pcell. Am I missing something? Is there any option/switch in Assura that I have not enabled/disabled?

I tried another procedure to simulate my circuit, but I am not sure if that is a correct way. I did the complete layout and then I removed the MOSFETs from the layout, and inserted pins on the nets that were connecting to the MOSFET terminals. In the top-level testbench, I included the MOSFETs as schematic instances. Then, I ran the simulation using extracted view of the layout (minus the MOSFETs) and the MOSFET schematic models.

I would love to hear your comments on the accuracy of this procedure.

Thanks
Vipul