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Design Languages >> Verilog-AMS >> 2 phase clock generator w/o hidden state?
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Message started by huber on Oct 14^th, 2005, 5:05pm

Title: 2 phase clock generator w/o hidden state?
Post by huber on Oct 14^th, 2005, 5:05pm

Hello all-
I have written a two-phase clock generator in Verilog-A that generates clock waveforms with continuous derivatives. As I understand it, a discontinuous derivative causes spectre to revert to less accurate integration methods, which can cause problems in high resolution ADC simulations. I am using the function y(x) = tanh(x) - x*(1-tanh(3)) for the transition, which has zero derivative at x=-3 and x=3. Unfortunately, x is a hidden state, so the cell is incompatible with spectreRF. I have other hidden states too since I keep track of input clock edges. Anyone have any ideas on how to eliminate the hidden state? Is there a better way to approach the problem? I would like to have the clock frequency defined by a sinewave input. I tried to post the module but apparently it's too long. Still, any help is appreciated.
-Dan

Title: Re: 2 phase clock generator w/o hidden state?
Post by Jess Chen on Oct 14^th, 2005, 7:04pm

Why is x a hidden state? A function that has no memory (present output depends on present input) has no hidden state. Is x used somewhere else that makes it a hidden state? If so, if you explain what makes it a hidden state perhaps we can come up with a SpectreRF compatible solution. My favorite solution to hidden state problems is to abuse the resettable integrator.

Title: Re: 2 phase clock generator w/o hidden state?
Post by huber on Oct 15^th, 2005, 4:16pm

OK, lets simplify the problem. I want a module that, when the input crosses a threshold, transitions the output. I can think of no way to do this without capturing and storing the time at which the input crossed the threshold.

Title: Re: 2 phase clock generator w/o hidden state?
Post by huber on Oct 15^th, 2005, 5:46pm

Info on hidden state for anyone not familiar with this problem:
www.designers-guide.org/Analysis/hidden-state.pdf

Title: Re: 2 phase clock generator w/o hidden state?
Post by Ken Kundert on Oct 15^th, 2005, 5:48pm

Code:

@(cross(V(in)))
;
V(out) <+ transition((V(in) > 0) ? +1 : -1), 0, 0);

Alternatively, if your model is used to drive the RF circuit, you can try using the "instrument_module" attribute, described in http://www.designers-guide.org/Forum/?board=circuit;action=display;num=1127843168;start=9#9.

-Ken

Title: Re: 2 phase clock generator w/o hidden state?
Post by huber on Oct 15^th, 2005, 5:55pm

Hi Ken. Yes, the transition function works. But what if I want a continuous derivative?

Title: Re: 2 phase clock generator w/o hidden state?
Post by huber on Oct 15^th, 2005, 6:09pm

I'm using IC5033, so I guess the instrument_module attribute isn't an option. What about ignore_state?

Title: Re: 2 phase clock generator w/o hidden state?
Post by Ken Kundert on Oct 15^th, 2005, 11:23pm

A simple way to generate a two phase clock that has no hidden state and no discontinuities would be to just use two sinusoidal input sources with offset phases.

Would that work?

-Ken

Title: Re: 2 phase clock generator w/o hidden state?
Post by huber on Oct 17^th, 2005, 3:04pm

The important parameters that I want to capture in the model are:
1) nonoverlap time
2) rise time

With appropriately phase-shifted and DC-shifted (to get duty cycle < 50%) sinusoids I could place zero crossings to get the nonoverlap time correct. But I would still need the zero crossing of these sinusoids to trigger some sort of clean transition with the proper rise time. Again, I don't know how I can create such a transition waveform without storing the time of the zero crossing.

Title: Re: 2 phase clock generator w/o hidden state?
Post by Jess Chen on Oct 17^th, 2005, 4:42pm

I suspect that an integrator could do the job. SpectreRF has access to the integrator state. You could integrate different constants, including zero, depending on the level of a sinusoidal drive. You might have to be careful about initial conditions. You might also want to some how work in a period reset to limit error accumulation.

-Jess

Title: Re: 2 phase clock generator w/o hidden state?
Post by rf-design on Oct 17^th, 2005, 10:15pm

If the 2-phase signals should be derived from a sinewave input the best way is to model a divide by 2 circuit, which generate 2-phases with 90 degree relationship. The model have to use two integrators with positive feedback and crosscoupling controlled by the sinewave input. That is the basic model of a two latches.

Title: Re: 2 phase clock generator w/o hidden state?
Post by huber on Oct 18^th, 2005, 11:37am

Ahh, that sounds promissing. So a divide-by-2 will give me quadrature signals, and I could get the correct duty cycle with a DC shift. Using a DC shift isn't the cleanest way since the nonoverlap time will depend on the input frequency, but I guess it would work. Any other ideas on how to generate the nonoverlap time? What about using a lowpass RC circuit for delay? This would delay the zero crossings by tau=RC, right? There is still the problem of generating a clean output transition, but I should probablly worry about one thing at a time.

Title: Re: 2 phase clock generator w/o hidden state?
Post by rf-design on Oct 18^th, 2005, 10:53pm

I think also a nonoverlapping clock generator could be modelled with nonlinear controlled differential equations. I used the model for Simulink and VHDL-AMS to model a divide by 2 operating in the RF domain.