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Design Languages >> Verilog-AMS >> Test for the divider Mode without Hiddenstate
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Message started by tumeda on Oct 18^th, 2005, 6:35am

Title: Test for the divider Mode without Hiddenstate
Post by tumeda on Oct 18^th, 2005, 6:35am

Hi

I tried to test the divider model without hiddenstate. The Ken's model is directly used.
I am confused ???
Why the output voltage of the divider F_out is always 0V. The divider model seems to work not in order.
Any suggestion?

The testbench netlist is here

Code:

...
simulator lang=spectre
global 0
include "definitions.scs"
include "init.scs"
include "include.scs" section=nom
...
// View name: schematic
I1 (F_out net013 F_in net013) divideByN n=4 nhi=2 dir=1 vdd=1.5 vss=0 \
thresh=0.75
R0 (net013 F_out) resistor r=1K isnoisy=yes
V1 (net013 0) vsource type=dc dc=0 mag=0 phase=0
V0 (F_in net013) vsource type=pulse mag=0 phase=0 val0=0 val1=1.5 \
period=4n delay=0 rise=10p fall=10p width=2n
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=60n errpreset=conservative write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
pss pss fund=250M harms=3 errpreset=moderate tstab=40n
+ method=gear2only annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=all pwr=all currents=all useprobes=yes \
saveahdlvars=all
ahdl_include "/home/fcaprj/zou_c11/v0.0.0/units/main/cdb/PLL_CHP/dividerNoHiddenState/veriloga/veriloga.va"

The schematic of testbench is here:
http://img159.photo.163.com/zoujunjx/17445359/450870125.gif

Title: Re: Test for the divider Mode without Hiddenstate
Post by Ken Kundert on Oct 18^th, 2005, 9:50am

The default transition time (tt) is 10ms. That is not going to work with a 4ns input period. Set tt=1ns.

-Ken