The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> transfer function of a counter https://designers-guide.org/forum/YaBB.pl?num=1129966561 Message started by svensl on Oct 22nd, 2005, 12:36am

Title: transfer function of a counter Post by svensl on Oct 22nd, 2005, 12:36am Hello all, I am wanting to model a counter in a control loop with a transfer function so that I can apply control therory to examine stability. I am not quite sure what to use for a transfer function. The system is discrete time and the counter counts the input pules (random) before dumping them to its output. I have considered two possibilities so far: 1) the counter acts as an integrator and thus I could use 1/s or 1/(z-1) as TF. 2) the counter is a decimator and has the TF (1-z-N)/(1-z-1) I am not quite happy with version 1) as 1/(z-1) does not look at what happens in between sampling instances. Remember that the input pulses occure randomly without a time reference. The TF 1/s does not apply since the overall system is sampled. Version 2) has I guess the same issue and since there is no set decimation factor N, I don't think this equation applies. Does anyone have any suggestions, hints, comments... Thanks a lot, Sven

Title: Re: transfer function of a counter Post by Jess Chen on Oct 22nd, 2005, 11:14am I wonder if this isn't more a question of units. If your control system is working with pulses per some unit of time, then your counter is merely a sensor, not an integrator. It sounds like the pulses do not enter your counter at a constant rate. Is the sample rate of the rest of your system the same as the rate at which your counter outputs data? If so, then I don't see the counter as a decimator either. So if you are trying to control pulse rate and the rest of the system works at the same sample rate as the counter output, then perhaps your counter is just a gain block that measures pulse rate.

Title: Re: transfer function of a counter Post by svensl on Oct 23rd, 2005, 1:07am Jess Chen, Thanks for your feedback. Indeed the pulses enter the counter without any constant rate. The counter output, however, occurs at a constant rate Ts which is the rate the overall system is clocked. To model the counter as a simple gain block does not suffice as it does not give insight into stability. An analogy would be a quantizer. A quantizer is sometimes modeled with a variable gain and a phase shift to obtain the systems overall stability (i.e. sigma delta modulators). A constant gain does not provide such insight. So I am looking to find a TF for a counter wich counts input  pulses and the dumps them after a constant rate to the output. Thanks a lot for any help. Sven

Title: Re: transfer function of a counter Post by Jess Chen on Oct 23rd, 2005, 10:53pm Sven, Is the counter measuring pulse rate and is that what you are trying to control? If so, given that the output sample rate is fixed and the pulse count is an integer, why wouldn't you model the coutner as a quantization block, as you described? For large signal stability, I think I would ignore the quantizer. For small signal stability, if there is any integration in the loop you will probably have a limit cycle and want to analyze its frequency. For that, you could treat the quantizer as a bang-bang controlling element. Another approach to analyzing nonlinear elements is the describing function. Yet another approach is to use ensemble averaging with knowledge of the distribution of the counter input to derive a nonlinear but continuous transfer curve relating input and output averages. Describing functions and bang-bang controllers are well documented for continuous time systems. I supose there might be a way to adapt them to discrete time systems. But you might be able to approximate the discrete time system with a continuous time system using a bilinear transformation to go from the z-domain to the s-domain. Regardless of how you decide to model the system, I would check the analysis against time domain simulations. I am not sure this helps. What does the rest of the system look like? What is the system you are trying to analyze?

Title: Re: transfer function of a counter Post by svensl on Oct 24th, 2005, 2:12am I would like to obtain a quantized representation of the input signal which is a frequency modulated signal. That is why I choose a counter. I am sort of familiar with the describing function method. As mentioned above the quantizer can then be modelled with variable gains and with phase uncertainty. But I could not use the same methods for the counter as it has essentially a pulse train with variable frequency at its input (information is in frequency), and a quantized output at a constant frequency where the information is now in amplitude. A variable gain does not apply here even if we assume the output amplitude to be constant, i.e. just a one bit counter. I will have a look in to ensemble averaging. Do you have any good references on ensemble averaging? Thanks for your help Jess Chen.

Title: Re: transfer function of a counter Post by Jess Chen on Oct 24th, 2005, 11:10pm I'm not sure I fully understand your application but here's a reference that uses the ensemble averaging I mentioned, although I don't recall if that's what they called it. -Jess Analysis and modeling of bang-bang clock and data recovery circuits Jri Lee   Kundert, K.S.   Razavi, B.   Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA This paper appears in: Solid-State Circuits, IEEE Journal of Publication Date: Sept. 2004 Volume: 39 , Issue: 9 On page(s): 1571 - 1580 ISSN: 0018-9200 INSPEC Accession Number:8113045 Digital Object Identifier: 10.1109/JSSC.2004.831600 Posted online: 2004-08-30 15:04:41.0

Title: Re: transfer function of a counter Post by Frank Wiedmann on Oct 24th, 2005, 11:30pm Just in case you are not aware of it: This article can be downloaded from Ken's personal website at http://www.thekunderts.net/ken/docs/jssc04-09.pdf. You can find a list of his publications at http://www.thekunderts.net/ken/pubs.html, most of them are available for download.

Title: Re: transfer function of a counter Post by svensl on Oct 31st, 2005, 4:33am The reference provided on bang-bang controllers where quite interesting but did not really help me solve my problem. Since a counter is essentially an integrator, I am looking for a continuous time equation (laplace domian) to model a resettable integrator. Any thought on this are greatly appreciated. Regards, Sven

Title: Re: transfer function of a counter Post by Jess Chen on Oct 31st, 2005, 7:30am Laplace domain transfer functions are usually applied only to linear time invariant systems. Are you sure that's what you have? -Jess

Title: Re: transfer function of a counter Post by svensl on Oct 31st, 2005, 7:30am Does anyone have the paper "A Nonlinear Integrator for Servomechanisms" by Clegg. It is from 1958 and I just cannot find a copy on the net. In it, Clegg talks about resettable integrators and that they have a phase lag of 38.1 degrees. I  don't know how he came up with that value. Does anyone here know? Cheers, sven Ps. Jess Chen, I agree with you. But I think cont. time is more suitable as discrete time does not look at all time instances. If a integrator is being reset by it's own state, as with clegg integrators, then the equation describing it should be continous.

Title: Re: transfer function of a counter Post by svensl on Nov 1st, 2005, 3:22am I found the answer to the Clegg integrator. When excited with a Asin(wt) input, the output of a Clegg integrator will be A/w*(1-cos(wt)). Using the describing function method, we can find the fourier coefficients. They equate to be a1=-A/w and b1=4A/(pi*w). Thus the transfer function is given as b1+j*a1 which will have a phase of 38.1 (pi/4) degrees.

Title: Re: transfer function of a counter Post by svensl on Nov 1st, 2005, 8:30am Having thought about the Clegg integrator, which resets its internal state every time its input is zero, makes me wonder whether a VCO has 90 degrees phase lag or less? I am asking since, at least in the model, a VCO performs a mod function. Thus it resets everytime the state hits 2pi. Is it right then to assume that a VCO might not have exactly 90 degrees phase lag?   Thanks

Title: Re: transfer function of a counter Post by Jess Chen on Nov 1st, 2005, 1:30pm Sven, I agree that the VCO resets but I would point out two observations: 1. Since the argument of the VCO can be thought of as a trig function, the "reset" events are transparent to the VCO output. It is only at the phase detector that such events become important. 2. In a phase domain model of the VCO, where the output is a sawtooth waveform, the output is not a true steady state quantity. I usually pull the VCO integrator, and the reference integrator, into the PFD model. This has couple of advantages. First, small signal analysis is performed about a true DC quantity (i.e. frequency). And since the DC analysis is valid, the models of the various components can be written to map out lock ranges with just the DC analysis. Second, by placing the integrator (a resettable integrator to be more precise) inside the PFD, the PFD accurately models the hysteresis observed in the relationship between average output and input phase error. Furthermore, the reset value of the integrator can be adjusted to accurately simulate the frequency slewing properties of the PFD. Where was I going with this? In a phase domain model, I think the resettable integrator belongs in the PFD, not the VCO. Furthermore, for small signal analysis, the integrator indeed introduces 90 degrees of phase lag. For large signal analysis, the behavior is highly nonlinear, probably to the point that the usual nonlinear methods, such as describing functions, bear little fruit.

Title: Re: transfer function of a counter Post by svensl on Nov 2nd, 2005, 12:15am Thanks for the response Jess Chen. I am not quite certain whether I understood your answer, so please let me try to ask different question which might shed some more light. I was asking whether a VCO might  have a different phase lag than a conventional integrator as when I have a negative feedback loop with two integrators in the feed forward path  (1/s^2), then the system will go unstable. Notice there is no feedback path in between the two integrators. However, if I replace the second integrator with a VCO, then the loop is stable. If the VCO acts as an ideal integrator, inheriting all its properties, why then is the loop stable? I am sure it due to the mod function that is inherent to VCO’s which will not saturate the system but I might be wrong here. Cheers, Sven

Title: Re: transfer function of a counter Post by Jess Chen on Nov 2nd, 2005, 11:37am Sven, It is too bad we could not meet face to face.  It seems we are both having trouble communicating. Im the California and based on when you respond, I suspect you are in Europe. Before I explain my response, let me ask a couple of questions. 1. Are you working with a PLL? 2. When you replace the ideal integrator with a VCO, I assume you are also switching between phase domain and voltage domain models. Right? 3. Exactly how are you distinguishing between stability and instability? -Jess

Title: Re: transfer function of a counter Post by svensl on Nov 3rd, 2005, 2:32am Jess Chen, I sent you an email with a detailed description including some figures explaining what I am trying to achieve. This might help clear things up a bit. Please feel free to contact me via email as well. I will post any outcome so that others can benefit from it as well. Regards, Sven

Title: Re: transfer function of a counter Post by Jess Chen on Nov 3rd, 2005, 10:26am Sven, I looked over the picture you sent me. I come back to one of my earlier comments. First, I assume the counter is reset after dumping it's output. If that is true, then I don't believe the combination of the VCO and counter constitute an integrator. Instead, I believe it is a quantizer. If the counter never reset itself, I think the VCO/counter would be an integrator. The output would be total number of pulses. However, if the counter indeed resets after every sample, the output is pulses PER sample period, which is a rate. Rate computation is a differentiation process, one that cancels out the integration inside the VCO. I believe that is why your system is unstable when you replace the VCO/counter with an integration. In one case, you have an integration. In the other you have an integration followed by a differentiation. -Jess

Title: Re: transfer function of a counter Post by svensl on Nov 3rd, 2005, 12:22pm With respect to your last post you wrote: "First, I assume the counter is reset after dumping it's output. If that is true, then I don't believe the combination of the VCO and counter constitute an integrator. Instead, I believe it is a quantizer." Well, it should be integration and quantization. The VCO by itself constitutes an integrator. The counter performs the quantization over the sampling period before being reset. In essence, the counter qunatizes the input signal to the VCO. If the input voltage to the VCO is higher, the VCO frequency will be higher, thus the counter will count more pulses, and thus the count value will be higher. Quantization. But you make also a valid point when saying that the counter is a diff. as its output gives the rate or pulses per sampling period. This would indeed explain the stability of the system. What would be a good way of modeling the counter with a variable transfer function to investigate limit cycles and stability issues for different signal magnitudes? Thank you so much for this inspiring conversation Jess Chen. Regards, Sven

Title: Re: transfer function of a counter Post by Jess Chen on Nov 3rd, 2005, 4:20pm Sven, I think the VCO/counter combination is essentially a quantizer with a one sample delay. For limit cycle analysis, let's consider two cases: 1. The VCO frequency is a harmonic of the sample rate. In this case, the steady state output of the counter is constant. 2. The VCO frequency is not a harmonic of the sample rate. Now the error in the quantized pulse rate accumulates until the counter outputs an extra pulse. I think this is how the integrating nature of the VCO manifests itself in this system. The counter output toggles between two values with a duty cycle related to the ratio of the nearest harmonic of the sample rate, that is still less than the VCO frequency, and the VCO frequency. In one sense, the VCO/counter is unstable all by itself because it toggles indefinitely. I will have to think longer about what happens when we close the loop. One way to model it is to treat the VCO/counter as an ideal quantizer, with one delay, that has a deterministic periodic signal injected related to the ratio of the VCO frequency and sample rate. The injected periodic signal has an amplitude of one pulse. I don't think the injected signal will affect closed loop stability. I think it is more of an "external" disturbance. -Jess

Title: Re: transfer function of a counter Post by svensl on Nov 4th, 2005, 3:20am Jess, One could indeed replace the VCO+counter by an integrator+qunatizer and then apply conventional methods to analyze limit cycles. However, the counter might have different properties that might not be observable when replacing it. So I am looking at a way to relate the input to the output. Assume we are talking about a 1-bit counter, then in order to have the same magnitude (count value) regardless of the input, we need to change the reset frequency of the counter. So with increasing pulse frequency of the input, the reset frequency needs to be increased, or equivalently the ratio of the VCO frequency to sampling/reset frequency needs to be constant. But what model could this be? Sven

Title: Re: transfer function of a counter Post by Jess Chen on Nov 4th, 2005, 8:53am Sven, I am not sure I understand your question but I think you are asking how one could model the toggling behavior of the VCO/counter when its input is held constant. I suspect you might be able to model this behavior with a phase detector operating on the VCO frequency some harmonic of the sampling clock.  Perhaps a modulo operation on the VCO frequency would take care of knowing which sampling clock harmonic to use. -Jess

Title: Re: transfer function of a counter Post by svensl on Nov 4th, 2005, 10:26am Sorry for not being clear enough, I guess I was just writing out my thoughts. Jess, you know when a quantizer is modeled in a modulator to investigate the systems stability, it is often replaced by a variable gain and phase uncertainty. So for example, when the input to the quantizer is small the quantizer gain has to be large to have the output magnitude stay constant at +/-1. When the input signal is large, the quan. gain will be small. Now, with the counter things are a bit different. If we assume a 1-bit counter then the output of the counter will be 0 or 1, Thus, the output magnitude is constant just like in the quantizer case. However, the input to the counter is a pulse train with variable frequency. Therefore, I was suggesting a model that will change the reset frequency of the counter so that no matter how high the frequency at the input is, the output will never be able to count to 2, for example. This is the only way I can think of modeling the non-linearity of the counter, but again I don't know what sort of function could do. In your last post you wrote: "I am not sure I understand your question but I think you are asking how one could model the toggling behavior of the VCO/counter when its input is held constant. " What kind of information would I be able to obtain from such a model where is input is held constant? I guess  it would display idle tones and limit cycles in the spectrum. Regards, Sven

Title: Re: transfer function of a counter Post by Jess Chen on Nov 4th, 2005, 4:40pm Sven, Does your counter only have one bit or are you just trying to model the toggling of the last bit? On the variable sample rate, in the system (not the model), is it fixed or variable? I only mentioned a constant input to focus on the toggling behavior. My point is that I think the VCO/counter output oscillates all by itself, without any feedback, unless the VCO and sample rate are harmonically related.  But I think we agree on that. -Jess

Title: Re: transfer function of a counter Post by svensl on Nov 5th, 2005, 12:33am Jess, "Does your counter only have one bit or are you just trying to model the toggling of the last bit?" I was just trying to make it more simple by assuming 1-bit only and to make it easier to compare to the 1-bit qunatizer case. It does not have to have only one bit. By changing the reset frequency you can change it accumulation and therefore the bits. (providing the counter can cope). "On the variable sample rate, in the system (not the model), is it fixed or variable?" The VCO being continuous, the only sampling (resetting) occurs at the counter, which is constant. "I only mentioned a constant input to focus on the toggling behavior. My point is that I think the VCO/counter output oscillates all by itself, without any feedback, unless the VCO and sample rate are harmonically related.  But I think we agree on that." Since the counter is a differentiator there is indeed no need for a feedback signal. And yes, when the input is kept constant then the output of the counter will have a repetitive sequence. Regards, Sven

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