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Design >> RF Design >> questions about test of PLL and VCO
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Message started by chip on Oct 22^nd, 2005, 8:11am

Title: questions about test of PLL and VCO
Post by chip on Oct 22^nd, 2005, 8:11am

1.about I/O circuit,How to choose the PAD for test?Beacause of the high speed output,do I have to choose LVDS PAD?
and is the speed of the I/O important?If i decide to design PAD myself,what should I pay special attention for?
2.about package,because of the high speed output,do I have to use flip chip package?
Could I use normal package and LVDS PADs,then construct circuit at board level to recovery the signal?
3.how will the problems above and the measurement instrument influence the measurement of the jitter of our PLLand VCO

thanks a lot:)

Title: Re: questions about test of PLL and VCO
Post by Paul on Oct 24^th, 2005, 12:10am

Hi,

LVDS typically runs at 622Mb/s, which may not be fast enough if you are designing common RF PLLs. You will probably have to design your own output driver (taking care of the parasitics it will see at the output) and use an analog-type pad. Also consider normal analog pads may include a consequent capacitive load due to ESD protection.
If you are in the prototyping stage, a chip-on-board solution may be less expensive compared to flip-chip mounting.
RF measurement equipement typically has 50 Ohm load, so you have to design a driver which can deliver enough current to that load.

Paul

Title: Re: questions about test of PLL and VCO
Post by chip on Oct 24^th, 2005, 6:14am

thank for ur reply first :)
what is "analog PAD" do you mean?
you mean that maybe I can design an drive buffer to drive the "analog PAD",so looks like below
------ ----------------- －－－－－----
|PLL|----|output driver|---|analog pad|
|___| |__________| |_________|
is there any misunderstanding by me?
actually I'm considering to do the measurement on the way of wafer testing so that it can avoid the disturbance by the package.then have i design the PAD and ESD circuits?

Title: Re: questions about test of PLL and VCO
Post by Paul on Oct 24^th, 2005, 1:15pm

I thought you were using a conventional padring. In that case, by "analog pad" I mean a bonding pad without buffer circuitry usually included in digital pads, or like in LVDS pads. Your drawing corresponds to what I meant.

In case you do wafer probing, your driver design doesn't require the same strength, but you probably still need it. Concerning ESD protection, it is always preferrable to have some, but for prototyping you can probably keep it small.

Paul