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Simulators >> Logic Simulators >> Verilog help
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Message started by engineer21 on Oct 23^rd, 2005, 7:21pm

Title: Verilog help
Post by engineer21 on Oct 23^rd, 2005, 7:21pm

Hello all,

Can somebody help me with Verilog programming. I am using Xilinx to program and modelsim to simulate. The problem I am having is in the module named add_or_subtract. What I am trying to do is compare the check_next_bit with check_bit. Check_bit is being passed in and check_next_bit is assigned a value of 0. These are some of the errrors that I get :"Reference to scalar reg 'check_next_bit' is not a legal net lvalue","Illegal left hand side of continuous assign". I need to assign values to a and s with the if statements then what ever i get from there I will assign them to add and sub. Can somebody help me:

module not working:
module add_or_subtract(check_bit,add,sub);
input check_bit;
output add,sub;
reg check_next_bit,bit;
reg a,s;

assign check_next_bit= 0;
assign bit = 1;
assign a=0;
assign s=0;

always @(bit) begin

if(check_bit<=check_next_bit)
begin
a = 1;
s = 0;
end
else if (check_bit>=check_next_bit)
begin
a = 0;
s = 1;
end
end
assign sub=s;
assign add=a;
endmodule

Entire program
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:12 10/23/05
// Design Name:
// Module Name: new_booth
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module new_booth(clk,go,in_bus,out_bus,multiplicand_twos,add,sub);

input [3:0] in_bus;
input clk,go;
output [3:0]out_bus,multiplicand_twos;
reg [3:0] multiplier;
reg [3:0] multiplicand;
output add,sub;
always @ (posedge go)
begin
assign multiplier = in_bus;
//assign a[15:8] = a[7];
end
always @(posedge clk)
begin
assign multiplicand = in_bus;
//assign b[15:8] = b[7];
end

twos_comp one(multiplier,multiplicand_twos);
add_or_subtract f0(multiplier[0],add,sub);
endmodule
////////////////////////////////////////////////////////////////////////////////
module twos_comp(m,n);
input [3:0] m;
output [3:0] n;
assign n=(~m) + 4'b0001;

endmodule
///////////////////////////////////////////////////////////////////////////////
module add_or_subtract(check_bit,add,sub);
input check_bit;
output add,sub;
reg check_next_bit,bit;
reg a,s;

/*
assign check_next_bit= 0;
assign bit = 1;
assign a=0;
assign s=0;
*/

always @(bit) begin

if(check_bit<=check_next_bit)
begin
a = 1;
s = 0;
end
else if (check_bit>=check_next_bit)
begin
a = 0;
s = 1;
end
end
assign sub=s;
assign add=a;
endmodule

Title: Re: Verilog help
Post by Andrew Beckett on Oct 24^th, 2005, 1:00pm

You're trying to use a continuous assign with registers - which can't be done. Either it's a continuous assign (and you don't need the reg) - or you need to just do the assign at the beginning of the simulation.

The code below will work:

Code:

module add_or_subtract(check_bit,add,sub);
input check_bit;
output add,sub;
//reg check_next_bit,bit;
reg a,s;

assign check_next_bit= 0;
assign bit = 1;
initial begin
assign a=0;
assign s=0;
end

always @(bit) begin

if(check_bit<=check_next_bit)
begin
a = 1;
s = 0;
end
else if (check_bit>=check_next_bit)
begin
a = 0;
s = 1;
end
end
assign sub=s;
assign add=a;
endmodule

In the above, since check_next_bit and bit only get assigned once, it's OK for them to be continuous assigns. But a and s need to be changed throughout the simulation, so these need to be registers. So using an initial block is the way to do this.

Regards,

Andrew.