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Other CAD Tools >> Physical Verification, Extraction and Analysis >> auLvs Creation
https://designers-guide.org/forum/YaBB.pl?num=1130931641

Message started by maxtheshark on Nov 2^nd, 2005, 3:40am

Title: auLvs Creation
Post by maxtheshark on Nov 2^nd, 2005, 3:40am

Hi,
I'm trying to made a parametrized cell to design an integrated inductor using skill. The layout is correctely generated using the CDF parameters mask in Virtuoso Environmet, but when I include this component in an higher level hierarchy cellview and I run the LVS, Diva doesn't recognize the Inductor component. I guess the cellview auLvs must be created for the inductor component, but I don't know how to generate this cellview. I checked in Cadence Documentation but I didn't find any reference.
Can you help me?

Title: Re: auLvs Creation
Post by bernd on Nov 9^th, 2005, 10:45am

The 'auLvs' view is nothing more than a stopping view
for the Diva netlister. Which means this view is needed
for schematic netlist generation
if you netlist with CDS_Netlisting_Mode=Analog.
The default switch view list here is ("auLvs" "schematic" ).
If you miss that view you should probably get a warning by Diva similar to
these:
Cannot find switch master cell for instance etc. ...

Anyhow you can create a auLvs view if you simply copy your
symbol view to the name auLvs, but you should be aware that
the Diva netlister stops then at this cell and makes an netlist entry.

BUT as on your description I assume
that your problem is caused on the layout side and your
inductor is not recognized by the device extraction.
Have you checked your extracted view if there is an inductor included
and your divaEXT.rul file if inductors are covered here!

Bernd