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Design >> High-Speed I/O Design >> Request paper/doc on digital CDR loop analysis
https://designers-guide.org/forum/YaBB.pl?num=1130937652

Message started by neoflash on Nov 2^nd, 2005, 5:20am

Title: Request paper/doc on digital CDR loop analysis
Post by neoflash on Nov 2^nd, 2005, 5:20am

I really dazzle before loop analysis of digital CDR.

Those up/down converters, ripple counters, voters.

How to analyze them for those loop parameters, such as loop bandwidth, phase margin?

thanks,
Neoflash

Title: Re: Request paper/doc on digital CDR loop analysis
Post by Paul on Nov 2^nd, 2005, 11:22am

Hello,

I guess you are talking about bang-bang clock recovery. If so, a nice introduction can be found here:
http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf

This is also part of the tutorials in B.Razavi's latest collection of papers.

If you want more detailed answers, please formulate your questions accordingly.

Paul

Title: Re: Request paper/doc on digital CDR loop analysis
Post by neoflash on Nov 3^rd, 2005, 12:06am

thanks for the information.

I am trying to analyze detailed performance of digital CDR loop, based on Alexander PFD.

I want to calculate loop bandwidth, jitter peaking, stability damping factor, and etc.

It is not hard for analog loop filter and VCO. However, all filters are digital and these is phase interpolator instead of VCO.

Thus, I need some ref doc to start with.

many thanks,
Neoflash

Title: Re: Request paper/doc on digital CDR loop analysis
Post by Paul on Nov 3^rd, 2005, 1:22pm

The above-mentioned documentation addresses the issues you mention, except that it considers bang-bang PLLs and not phase interpolation CDRs. For more information on BB-PLL CDRs, you can also look for papers by Y. Greshichev.

Concerning phase interpolation structures, the following reference may serve as a starting point:
"A semidigital dual delay-locked loop"
Sidiropoulos, S.; Horowitz, M.A.;
Solid-State Circuits, IEEE Journal of
Volume 32, Issue 11, Nov. 1997 Page(s):1683 - 1692

Best,

Paul