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Design Languages >> Verilog-AMS >> Analog bus limitation, any work-around ?
https://designers-guide.org/forum/YaBB.pl?num=1131166523

Message started by ekne on Nov 4^th, 2005, 8:55pm

Title: Analog bus limitation, any work-around ?
Post by ekne on Nov 4^th, 2005, 8:55pm

Hi
Using AMS Designer and want to do:

electrical amx;
real V_amx_3;
real V_amx_2;
initial begin

#50;
V_amx_3 = V(amx[3]);
V_amx_2 = V(amx[2]);
etc.....

but get an ncelab error that this is not supported i.e.
analog bus in "digital domain".

So is there a way to work-around this ?

Not, talking about changing the schematic to not use an
analog bus i.e. define two separate signals.

Why isn't this supported, don't really see why it should
be a limitation at all.
(spice/digital busbit notations < vs [ ? perhaps ? but
that shouldn't be a limitation)

Thanks //BEE

???

Title: Re: Analog bus limitation, any work-around ?
Post by jbdavid on Nov 9^th, 2005, 9:26am

I wrote up a great idea, thats NOT the answer to your problem..

Yes workaround is easy.. don't do the conversion in the logic domain.. do it in the analog block..

Title: Re: Analog bus limitation, any work-around ?
Post by jbdavid on Nov 9^th, 2005, 9:31am

ie:

electrical amx;
real V_amx_3;
real V_amx_2;
analog begin
@(timer(50n)) begin
// this is a ONE time event, like initial block
// initial begin
// #50;
V_amx_3 = V(amx[3]);
V_amx_2 = V(amx[2]);
etc.....

Title: Re: Analog bus limitation, any work-around ?
Post by Andrew Beckett on Nov 15^th, 2005, 11:12am

Hi BEE,

There's a PCR for this - 295207. It's an implementation limitation at the moment - I've asked for a status update on this PCR.

Regards,

Andrew.

Title: Re: Analog bus limitation, any work-around ?
Post by ekne on Nov 15^th, 2005, 7:31pm

Thanks Mr Andrew
I thought I give this forum a try. Very interesting one.
Will keep on returning to it. ::)

Thanks again.
//BEE