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Design Languages >> Verilog-AMS >> The methods to avoid the negative delay time
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Message started by tumeda on Nov 17^th, 2005, 1:40am

Title: The methods to avoid the negative delay time
Post by tumeda on Nov 17^th, 2005, 1:40am

Hello,
I would like to discuss about delay time in the modeling of CP. (Listing 10 in paper jitter+phase noise)
"
...
parameter real td= 200e-12;
parameter real jitter=20e-12;
...
dt=jitter*$dist_normal(seed,0,1);
...
I(out)<+transition(Iout*state, td+dt,tt)
...
"
The vaule of the delay time, i.e. td+dt, should avoid negative. There are two metods to aovid that.
Method 1 :
Set the "td" enough large, e.g. 500e-12 or even larger. I would like to confirm my question: Does the delay time not influence the jitter calculation for the PLL. Because I though the delay times are same for all transition edges. Is it right???
Method 2 :
Set the delay time td= 3*jitter, and cut other values, if the td+dt is negative. Actually, the distribution is not true gaussian distribution, but the influence for jitter calculation is very small.
"...
if td+dt<0
td+dt=0;
end
I(out)<+transition(Iout*state, td+dt,tt)
"

Which method is better from your side? Any anser would be appreciate!!!