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Design Languages >> Verilog-AMS >> veriloga -> loop of rigid branches (shorts)
https://designers-guide.org/forum/YaBB.pl?num=1132929989

Message started by marben on Nov 25^th, 2005, 6:46am

Title: veriloga -> loop of rigid branches (shorts)
Post by marben on Nov 25^th, 2005, 6:46am

I would realise a polarisation stage in veriloga language.
I need to instantiate 80 similar polarisations stages (PolaStage<79:0>).
Each stage has the same input current (in) but not the same output voltage (out<79:0>).
So if I have a current source of 80µA, each stage see only 1µA.

To simplify my problem, I wrote :

>
> branch (in,gnd) toto
>
> analog begin
> outval = K * I(toto);
> V(out) <+ outval;
> end

the parser didn't see error but when I start spectre, I have a fatal error >:( :

The following branches form a loop of rigid branches (shorts) when added to the circuit :
PolaStage_0:in_flow (from in to 0)
PolaStage_1:in_flow (from in to 0)
PolaStage_2:in_flow (from in to 0)
PolaStage_3:in_flow (from in to 0)
....

Is it really impossible to write a veriloga close to the schematic in this case ??
Thanks for your help

Ben

Title: Re: veriloga -> loop of rigid branches (shorts)
Post by Andrew Beckett on Nov 27^th, 2005, 5:19am

The trouble is that each of your 80 current probes is essentially a zero-volt source between in and gnd - and so each of these are in parallel, and thus causes the loop of rigid branches.

You could put some impedance in series with the current probe, but I'm not sure that's really what you want - because are you really measuring the current properly then? Perhaps you need to separate the current measurement using (say) a current-controlled voltage source (e.g. a ccvs) and then connect the voltage output of this to all the 80 stages?

There's almost certainly other ways of solving this, but this was the first that came to mind (especially without knowing the details of what you're really trying to achieve).

Regards,

Andrew.

Title: Re: veriloga -> loop of rigid branches (shorts)
Post by Geoffrey_Coram on Nov 30^th, 2005, 12:39pm

I'd lean towards using a bus in the module

module polar(in, out);
inout in;
inout out[79:0];
electrical in;
electrical out[79:0];
parameter real K = 1;
real ibr;
genvar idx;

analog begin
ibr = I(in,gnd);
for (idx=0; idx<80; idx = idx + 1) begin
V(out[idx]) <+ K * ibr;
end
end
endmodule

If your gain K differs, then you'd need
parameter real K[79:0] = { };
and you'd need to put 80 values in the braces {}.

Title: Re: veriloga -> loop of rigid branches (shorts)
Post by marben on Dec 1^st, 2005, 1:43am

thanks for all.

Yes, it was a zero volt problem..
I put some input impedance and it work properly. The input current is create by another veriloga block and it is independant of the impedance.

ben

Title: Re: veriloga -> loop of rigid branches (shorts)
Post by Geoffrey_Coram on Dec 1^st, 2005, 3:55am

I'm still unsure whether the input current is supposed to be split among all 80 stages, or whether each one is supposed to depend on the full value (which is what my suggestion does).

I mention this for later readers of the forum, as you've solved your problem.